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-rw-r--r--src/northbridge/intel/e7501/Config.lb4
-rw-r--r--src/northbridge/intel/e7501/northbridge.c11
2 files changed, 15 insertions, 0 deletions
diff --git a/src/northbridge/intel/e7501/Config.lb b/src/northbridge/intel/e7501/Config.lb
index 59154f7ed3..2a8095f692 100644
--- a/src/northbridge/intel/e7501/Config.lb
+++ b/src/northbridge/intel/e7501/Config.lb
@@ -1,3 +1,7 @@
+uses HAVE_HIGH_TABLES
+
config chip.h
object northbridge.o
+
+default HAVE_HIGH_TABLES=1
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index b1d553aab1..7168bf3112 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -65,6 +65,11 @@ static uint32_t find_pci_tolm(struct bus *bus)
return tolm;
}
+#if HAVE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
@@ -140,6 +145,12 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, remapbasek,
(remaplimitk + 64*1024) - remapbasek);
}
+
+#if HAVE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
}
assign_resources(&dev->link[0]);
}