1 files changed, 28 insertions, 0 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c
index 6f1ce2f732..3f982c4a17 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c
@@ -37,6 +37,7 @@
 #include "chip.h"
 #include "northbridge.h"
 #include <fsp_util.h>
+#include <cpu/intel/smm/gen1/smi.h>
 
 static int bridge_revision_id = -1;
 
@@ -318,6 +319,33 @@ static void northbridge_init(struct device *dev)
 	printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
 }
 
+static u32 northbridge_get_base_reg(device_t dev, int reg)
+{
+	u32 value;
+
+	value = pci_read_config32(dev, reg);
+	/* Base registers are at 1MiB granularity. */
+	value &= ~((1 << 20) - 1);
+	return value;
+}
+
+void
+northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size)
+{
+	device_t dev;
+	u32 bgsm;
+	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+	*tsegmb = northbridge_get_base_reg(dev, TSEG);
+	bgsm = northbridge_get_base_reg(dev, BGSM);
+	*tseg_size = bgsm - *tsegmb;
+}
+
+void northbridge_write_smram(u8 smram)
+{
+	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram);
+}
+
 static struct pci_operations intel_pci_ops = {
 	.set_subsystem    = intel_set_subsystem,
 };