diff options
Diffstat (limited to 'src/northbridge/intel/fsp_sandybridge')
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/acpi.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/early_init.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/northbridge.h | 7 |
3 files changed, 11 insertions, 6 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c index a372e7b70b..bf23e65d10 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi.c +++ b/src/northbridge/intel/fsp_sandybridge/acpi.c @@ -120,7 +120,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion) optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios + oprom->vbt_offset); - if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) { + if (read32(vbt->hdr_signature) != VBT_SIGNATURE) { printk(BIOS_DEBUG, "VBT not found!\n"); return 1; } diff --git a/src/northbridge/intel/fsp_sandybridge/early_init.c b/src/northbridge/intel/fsp_sandybridge/early_init.c index 4b615e9dcd..f86690dc01 100644 --- a/src/northbridge/intel/fsp_sandybridge/early_init.c +++ b/src/northbridge/intel/fsp_sandybridge/early_init.c @@ -32,12 +32,12 @@ static void sandybridge_setup_bars(void) /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index d67d696d92..0432963ba5 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -49,10 +49,15 @@ /* Northbridge BARs */ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ +#ifndef __ACPI__ +#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ +#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ +#else #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#define DEFAULT_RCBABASE 0xfed1c000 +#define DEFAULT_RCBABASE ((u8 *)0xfed1c000) #if CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X #include <southbridge/intel/fsp_bd82x6x/pch.h> |