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path: root/src/northbridge/intel/haswell/mrc_misc.c
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Diffstat (limited to 'src/northbridge/intel/haswell/mrc_misc.c')
-rw-r--r--src/northbridge/intel/haswell/mrc_misc.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/src/northbridge/intel/haswell/mrc_misc.c b/src/northbridge/intel/haswell/mrc_misc.c
index de58ab9bfb..04707677cd 100644
--- a/src/northbridge/intel/haswell/mrc_misc.c
+++ b/src/northbridge/intel/haswell/mrc_misc.c
@@ -102,8 +102,8 @@ int fcn_fffbd29a(void * a0, void * a1, void * a2)
}
}
-int fcn_fffaa884(void *ram_data);
-int fcn_fffaa884(void *ram_data)
+int MrcFastBootPermitted(void *ram_data);
+int MrcFastBootPermitted(void *ram_data)
{
void *bar = *(void**)(ram_data + 0x103b);
@@ -964,7 +964,8 @@ fcn_fffb5038(void *ram_data,uint32_t *param_2,uint8_t *param_3,uint32_t *param_4
return memcfg_clk;
}
-int fcn_fffaa6af(void *ram_data)
+// fcn_fffaa6af
+int MrcRestoreNonTrainingValues(void *ram_data)
{
PRINT_FUNC;
@@ -1015,7 +1016,8 @@ extern uint8_t ref_fffcbc04[];
// CAPID0_A 0xe4 is already defined
#define CAPID0_B 0xe8
-int fcn_fffa78a0(void *ramdata)
+// fcn_fffa78a0
+int MrcMcCapabilityPreSpd(void *ramdata)
{
uint64_t lVar1;
uint32_t uVar2;
@@ -1127,7 +1129,8 @@ static bool is_zero256(const void *data)
return true;
}
-int fcn_fffb8689(void *ramdata)
+// fcn_fffb8689
+int MrcSpdProcessing(void *ramdata)
{
char cVar2;
uint32_t uVar4;
@@ -1144,7 +1147,7 @@ int fcn_fffb8689(void *ramdata)
local_78 = 0;
local_84 = 0;
local_7c = 0;
- local_80 = 0x16;
+ local_80 = 0x16; // mrcDimmNotExist
do {
iVar8 = local_78 * 0x2fa;
for (int idx = 0; idx < 2; idx++) {