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-rw-r--r--src/northbridge/intel/i3100/northbridge.c2
-rw-r--r--src/northbridge/intel/i3100/pciexp_porta.c2
-rw-r--r--src/northbridge/intel/i3100/pciexp_porta_ep80579.c2
-rw-r--r--src/northbridge/intel/i3100/raminit.c288
-rw-r--r--src/northbridge/intel/i3100/reset_test.c2
5 files changed, 148 insertions, 148 deletions
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index 8d37f3859c..c8e3221d65 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -46,7 +46,7 @@ static void pci_domain_set_resources(device_t dev)
printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
#endif
/* FIXME Me temporary hack */
- if(pci_tolm > 0xe0000000)
+ if (pci_tolm > 0xe0000000)
pci_tolm = 0xe0000000;
/* Ensure pci_tolm is 128M aligned */
pci_tolm &= 0xf8000000;
diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c
index 6ca7cfd972..71a2bf23a7 100644
--- a/src/northbridge/intel/i3100/pciexp_porta.c
+++ b/src/northbridge/intel/i3100/pciexp_porta.c
@@ -35,7 +35,7 @@ static void pcie_init(struct device *dev)
/* Get the chip configuration */
config = dev->chip_info;
- if(config->intrline) {
+ if (config->intrline) {
pci_write_config32(dev, 0x3c, config->intrline);
}
diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
index 2cc7bb1761..b5e35d6eac 100644
--- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
+++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c
@@ -36,7 +36,7 @@ static void pcie_init(struct device *dev)
/* Get the chip configuration */
config = dev->chip_info;
- if(config->intrline) {
+ if (config->intrline) {
pci_write_config32(dev, 0x3c, config->intrline);
}
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 443716f9ce..39e40e031e 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -63,7 +63,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
int max;
max = ARRAY_SIZE(register_values);
- for(i = 0; i < max; i += 3) {
+ for (i = 0; i < max; i += 3) {
device_t dev;
u32 where;
u32 reg;
@@ -162,7 +162,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
int i;
int cum;
- for(i = cum = 0; i < DIMM_SOCKETS; i++) {
+ for (i = cum = 0; i < DIMM_SOCKETS; i++) {
struct dimm_size sz;
if (dimm_mask & (1 << i)) {
sz = spd_get_dimm_size(ctrl->channel0[i]);
@@ -174,7 +174,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
cum += (1 << sz.side1);
/* DRB = 0x60 */
pci_write_config8(ctrl->f0, DRB + (i*2), cum);
- if( sz.side2 > 28) {
+ if ( sz.side2 > 28) {
sz.side2 -= 29;
cum += (1 << sz.side2);
}
@@ -189,7 +189,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask)
/* set TOM top of memory 0xcc */
pci_write_config16(ctrl->f0, TOM, cum);
/* set TOLM top of low memory */
- if(cum > 0x18) {
+ if (cum > 0x18) {
cum = 0x18;
}
cum <<= 11;
@@ -204,7 +204,7 @@ static u32 spd_detect_dimms(const struct mem_controller *ctrl)
u32 dimm_mask;
int i;
dimm_mask = 0;
- for(i = 0; i < DIMM_SOCKETS; i++) {
+ for (i = 0; i < DIMM_SOCKETS; i++) {
int byte;
u16 device;
device = ctrl->channel0[i];
@@ -235,7 +235,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
int cnt;
dra = 0;
- for(cnt=0; cnt < 4; cnt++) {
+ for (cnt=0; cnt < 4; cnt++) {
if (!(dimm_mask & (1 << cnt))) {
continue;
}
@@ -260,7 +260,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
if (value < 0) goto hw_err;
value = log2(value & 0xff);
reg += value;
- if(reg < 27) goto hw_err;
+ if (reg < 27) goto hw_err;
reg -= 27;
reg += (value << 2);
@@ -304,7 +304,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
drt = pci_read_config32(ctrl->f0, DRT);
drt &= 3; /* save bits 1:0 */
- for(first_dimm = 0; first_dimm < 4; first_dimm++) {
+ for (first_dimm = 0; first_dimm < 4; first_dimm++) {
if (dimm_mask & (1 << first_dimm))
break;
}
@@ -313,7 +313,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
drt |= (3<<18); /* Trasmax */
- for(cnt=0; cnt < 4; cnt++) {
+ for (cnt=0; cnt < 4; cnt++) {
if (!(dimm_mask & (1 << cnt))) {
continue;
}
@@ -322,7 +322,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
latency = log2(reg) -2;
/* Loop through and find a fast clock with a low latency */
- for(index = 0; index < 3; index++, latency++) {
+ for (index = 0; index < 3; index++, latency++) {
if ((latency < 2) || (latency > 4) ||
(!(reg & (1 << latency)))) {
continue;
@@ -330,8 +330,8 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
value = spd_read_byte(ctrl->channel0[cnt],
latency_indicies[index]);
- if(value <= cycle_time[drc&3]) {
- if( latency > cas_latency) {
+ if (value <= cycle_time[drc&3]) {
+ if ( latency > cas_latency) {
cas_latency = latency;
}
break;
@@ -339,36 +339,36 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
}
}
index = (cas_latency-2);
- if((index)==0) cas_latency = 20;
- else if((index)==1) cas_latency = 25;
+ if ((index)==0) cas_latency = 20;
+ else if ((index)==1) cas_latency = 25;
else cas_latency = 30;
- for(cnt=0;cnt<4;cnt++) {
+ for (cnt=0;cnt<4;cnt++) {
if (!(dimm_mask & (1 << cnt))) {
continue;
}
reg = spd_read_byte(ctrl->channel0[cnt], 27)&0x0ff;
- if(((index>>8)&0x0ff)<reg) {
+ if (((index>>8)&0x0ff)<reg) {
index &= ~(0x0ff << 8);
index |= (reg << 8);
}
reg = spd_read_byte(ctrl->channel0[cnt], 28)&0x0ff;
- if(((index>>16)&0x0ff)<reg) {
+ if (((index>>16)&0x0ff)<reg) {
index &= ~(0x0ff << 16);
index |= (reg<<16);
}
reg = spd_read_byte(ctrl->channel0[cnt], 29)&0x0ff;
- if(((index2>>0)&0x0ff)<reg) {
+ if (((index2>>0)&0x0ff)<reg) {
index2 &= ~(0x0ff << 0);
index2 |= (reg<<0);
}
reg = spd_read_byte(ctrl->channel0[cnt], 41)&0x0ff;
- if(((index2>>8)&0x0ff)<reg) {
+ if (((index2>>8)&0x0ff)<reg) {
index2 &= ~(0x0ff << 8);
index2 |= (reg<<8);
}
reg = spd_read_byte(ctrl->channel0[cnt], 42)&0x0ff;
- if(((index2>>16)&0x0ff)<reg) {
+ if (((index2>>16)&0x0ff)<reg) {
index2 &= ~(0x0ff << 16);
index2 |= (reg<<16);
}
@@ -376,22 +376,22 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
/* get dimm speed */
value = cycle_time[drc&3];
- if(value <= 0x50) { /* 200 MHz */
- if((index&7) > 2) {
+ if (value <= 0x50) { /* 200 MHz */
+ if ((index&7) > 2) {
drt |= (2<<2); /* CAS latency 4 */
cas_latency = 40;
} else {
drt |= (1<<2); /* CAS latency 3 */
cas_latency = 30;
}
- if((index&0x0ff00)<=0x03c00) {
+ if ((index&0x0ff00)<=0x03c00) {
drt |= (1<<8); /* Trp RAS Precharg */
} else {
drt |= (2<<8); /* Trp RAS Precharg */
}
/* Trcd RAS to CAS delay */
- if((index2&0x0ff)<=0x03c) {
+ if ((index2&0x0ff)<=0x03c) {
drt |= (0<<10);
} else {
drt |= (1<<10);
@@ -401,9 +401,9 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
drt |= (1<<12);
/* Trc TRS min */
- if((index2&0x0ff00)<=0x03700)
+ if ((index2&0x0ff00)<=0x03700)
drt |= (0<<14);
- else if((index2&0xff00)<=0x03c00)
+ else if ((index2&0xff00)<=0x03c00)
drt |= (1<<14);
else
drt |= (2<<14); /* spd 41 */
@@ -411,20 +411,20 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */
/* Trrd Row Delay */
- if((index&0x0ff0000)<=0x0140000) {
+ if ((index&0x0ff0000)<=0x0140000) {
drt |= (0<<20);
- } else if((index&0x0ff0000)<=0x0280000) {
+ } else if ((index&0x0ff0000)<=0x0280000) {
drt |= (1<<20);
- } else if((index&0x0ff0000)<=0x03c0000) {
+ } else if ((index&0x0ff0000)<=0x03c0000) {
drt |= (2<<20);
} else {
drt |= (3<<20);
}
/* Trfc Auto refresh cycle time */
- if((index2&0x0ff0000)<=0x04b0000) {
+ if ((index2&0x0ff0000)<=0x04b0000) {
drt |= (0<<22);
- } else if((index2&0x0ff0000)<=0x0690000) {
+ } else if ((index2&0x0ff0000)<=0x0690000) {
drt |= (1<<22);
} else {
drt |= (2<<22);
@@ -432,18 +432,18 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
/* Docs say use 55 for all 200MHz */
drt |= (0x055<<24);
}
- else if(value <= 0x60) { /* 167 MHz */
+ else if (value <= 0x60) { /* 167 MHz */
/* according to new documentation CAS latency is 00
* for bits 3:2 for all 167 MHz
drt |= ((index&3)<<2); */ /* set CAS latency */
- if((index&0x0ff00)<=0x03000) {
+ if ((index&0x0ff00)<=0x03000) {
drt |= (1<<8); /* Trp RAS Precharg */
} else {
drt |= (2<<8); /* Trp RAS Precharg */
}
/* Trcd RAS to CAS delay */
- if((index2&0x0ff)<=0x030) {
+ if ((index2&0x0ff)<=0x030) {
drt |= (0<<10);
} else {
drt |= (1<<10);
@@ -458,18 +458,18 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
drt |= (2<<16); /* Twr not defined for DDR docs say 2 */
/* Trrd Row Delay */
- if((index&0x0ff0000)<=0x0180000) {
+ if ((index&0x0ff0000)<=0x0180000) {
drt |= (0<<20);
- } else if((index&0x0ff0000)<=0x0300000) {
+ } else if ((index&0x0ff0000)<=0x0300000) {
drt |= (1<<20);
} else {
drt |= (2<<20);
}
/* Trfc Auto refresh cycle time */
- if((index2&0x0ff0000)<=0x0480000) {
+ if ((index2&0x0ff0000)<=0x0480000) {
drt |= (0<<22);
- } else if((index2&0x0ff0000)<=0x0780000) {
+ } else if ((index2&0x0ff0000)<=0x0780000) {
drt |= (2<<22);
} else {
drt |= (2<<22);
@@ -477,16 +477,16 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
/* Docs state to use 99 for all 167 MHz */
drt |= (0x099<<24);
}
- else if(value <= 0x75) { /* 133 MHz */
+ else if (value <= 0x75) { /* 133 MHz */
drt |= ((index&3)<<2); /* set CAS latency */
- if((index&0x0ff00)<=0x03c00) {
+ if ((index&0x0ff00)<=0x03c00) {
drt |= (1<<8); /* Trp RAS Precharg */
} else {
drt |= (2<<8); /* Trp RAS Precharg */
}
/* Trcd RAS to CAS delay */
- if((index2&0x0ff)<=0x03c) {
+ if ((index2&0x0ff)<=0x03c) {
drt |= (0<<10);
} else {
drt |= (1<<10);
@@ -501,25 +501,25 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
drt |= (1<<16); /* Twr not defined for DDR docs say 1 */
/* Trrd Row Delay */
- if((index&0x0ff0000)<=0x01e0000) {
+ if ((index&0x0ff0000)<=0x01e0000) {
drt |= (0<<20);
- } else if((index&0x0ff0000)<=0x03c0000) {
+ } else if ((index&0x0ff0000)<=0x03c0000) {
drt |= (1<<20);
} else {
drt |= (2<<20);
}
/* Trfc Auto refresh cycle time */
- if((index2&0x0ff0000)<=0x04b0000) {
+ if ((index2&0x0ff0000)<=0x04b0000) {
drt |= (0<<22);
- } else if((index2&0x0ff0000)<=0x0780000) {
+ } else if ((index2&0x0ff0000)<=0x0780000) {
drt |= (2<<22);
} else {
drt |= (2<<22);
}
/* Based on CAS latency */
- if(index&7)
+ if (index&7)
drt |= (0x099<<24);
else
drt |= (0x055<<24);
@@ -549,7 +549,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
/* 0x7c DRC */
drc = pci_read_config32(ctrl->f0, DRC);
- for(cnt=0; cnt < 4; cnt++) {
+ for (cnt=0; cnt < 4; cnt++) {
if (!(dimm_mask & (1 << cnt))) {
continue;
}
@@ -616,7 +616,7 @@ static void do_delay(void)
{
int i;
u8 b;
- for(i=0;i<16;i++)
+ for (i=0;i<16;i++)
b=inb(0x80);
}
@@ -637,18 +637,18 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
/* ODT enable */
pci_write_config32(ctrl->f0, SDRC, 0x30000000);
/* Figure out which slots are Empty, Single, or Double sided */
- for(i=0,t4=0,c2=0;i<8;i+=2) {
+ for (i=0,t4=0,c2=0;i<8;i+=2) {
c1 = pci_read_config8(ctrl->f0, DRB+i);
- if(c1 == c2) continue;
+ if (c1 == c2) continue;
c2 = pci_read_config8(ctrl->f0, DRB+1+i);
- if(c1 == c2)
+ if (c1 == c2)
t4 |= (1 << (i*4));
else
t4 |= (2 << (i*4));
}
- for(i=0;i<1;i++) {
- if((t4&0x0f) == 1) {
- if( ((t4>>8)&0x0f) == 0 ) {
+ for (i=0;i<1;i++) {
+ if ((t4&0x0f) == 1) {
+ if ( ((t4>>8)&0x0f) == 0 ) {
data32 = 0x00000010; /* EEES */
break;
}
@@ -663,8 +663,8 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
data32 = 0x77bbddee; /* SSSS */
break;
}
- if((t4&0x0f) == 2) {
- if( ((t4>>8)&0x0f) == 0 ) {
+ if ((t4&0x0f) == 2) {
+ if ( ((t4>>8)&0x0f) == 0 ) {
data32 = 0x00003132; /* EEED */
break;
}
@@ -686,14 +686,14 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
- for(dimm=0;dimm<8;dimm+=2) {
+ for (dimm=0;dimm<8;dimm+=2) {
write32(MCBAR+DCALADDR, 0x0b840001);
write32(MCBAR+DCALCSR, 0x81000003 | (dimm << 20));
- for(i=0;i<1001;i++) {
+ for (i=0;i<1001;i++) {
data32 = read32(MCBAR+DCALCSR);
- if(!(data32 & (1<<31)))
+ if (!(data32 & (1<<31)))
break;
}
}
@@ -717,18 +717,18 @@ static void set_receive_enable(const struct mem_controller *ctrl)
u32 work32h;
u32 data32r;
int32_t recen;
- for(dimm=0;dimm<8;dimm+=1) {
+ for (dimm=0;dimm<8;dimm+=1) {
- if(!(dimm&1)) {
+ if (!(dimm&1)) {
write32(MCBAR+DCALDATA+(17*4), 0x04020000);
write32(MCBAR+DCALCSR, 0x81800004 | (dimm << 20));
- for(i=0;i<1001;i++) {
+ for (i=0;i<1001;i++) {
data32 = read32(MCBAR+DCALCSR);
- if(!(data32 & (1<<31)))
+ if (!(data32 & (1<<31)))
break;
}
- if(i>=1000)
+ if (i>=1000)
continue;
dcal_data32_0 = read32(MCBAR+DCALDATA + 0);
@@ -744,56 +744,56 @@ static void set_receive_enable(const struct mem_controller *ctrl)
}
/* check if bank is installed */
- if((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
+ if ((dcal_data32_0 == 0) && (dcal_data32_2 == 0))
continue;
/* Calculate the timing value */
{
u32 bit;
- for(i=0,edge=0,bit=63,cnt=31,data32r=0,
+ for (i=0,edge=0,bit=63,cnt=31,data32r=0,
work32l=dcal_data32_1,work32h=dcal_data32_3;
(i<4) && bit; i++) {
- for(;;bit--,cnt--) {
- if(work32l & (1<<cnt))
+ for (;;bit--,cnt--) {
+ if (work32l & (1<<cnt))
break;
- if(!cnt) {
+ if (!cnt) {
work32l = dcal_data32_0;
work32h = dcal_data32_2;
cnt = 32;
}
- if(!bit) break;
+ if (!bit) break;
}
- for(;;bit--,cnt--) {
- if(!(work32l & (1<<cnt)))
+ for (;;bit--,cnt--) {
+ if (!(work32l & (1<<cnt)))
break;
- if(!cnt) {
+ if (!cnt) {
work32l = dcal_data32_0;
work32h = dcal_data32_2;
cnt = 32;
}
- if(!bit) break;
+ if (!bit) break;
}
- if(!bit) {
+ if (!bit) {
break;
}
data32 = ((bit%8) << 1);
- if(work32h & (1<<cnt))
+ if (work32h & (1<<cnt))
data32 += 1;
- if(data32 < 4) {
- if(!edge) {
+ if (data32 < 4) {
+ if (!edge) {
edge = 1;
}
else {
- if(edge != 1) {
+ if (edge != 1) {
data32 = 0x0f;
}
}
}
- if(data32 > 12) {
- if(!edge) {
+ if (data32 > 12) {
+ if (!edge) {
edge = 2;
}
else {
- if(edge != 2) {
+ if (edge != 2) {
data32 = 0x00;
}
}
@@ -806,43 +806,43 @@ static void set_receive_enable(const struct mem_controller *ctrl)
recen = data32r;
recen += 3;
recen = recen>>2;
- for(cnt=5;cnt<24;) {
- for(;;cnt++)
- if(!(work32l & (1<<cnt)))
+ for (cnt=5;cnt<24;) {
+ for (;;cnt++)
+ if (!(work32l & (1<<cnt)))
break;
- for(;;cnt++) {
- if(work32l & (1<<cnt))
+ for (;;cnt++) {
+ if (work32l & (1<<cnt))
break;
}
data32 = (((cnt-1)%8)<<1);
- if(work32h & (1<<(cnt-1))) {
+ if (work32h & (1<<(cnt-1))) {
data32++;
}
/* test for frame edge cross overs */
- if((edge == 1) && (data32 > 12) &&
+ if ((edge == 1) && (data32 > 12) &&
(((recen+16)-data32) < 3)) {
data32 = 0;
cnt += 2;
}
- if((edge == 2) && (data32 < 4) &&
+ if ((edge == 2) && (data32 < 4) &&
((recen - data32) > 12)) {
data32 = 0x0f;
cnt -= 2;
}
- if(((recen+3) >= data32) && ((recen-3) <= data32))
+ if (((recen+3) >= data32) && ((recen-3) <= data32))
break;
}
cnt--;
cnt /= 8;
cnt--;
- if(recen&1)
+ if (recen&1)
recen+=2;
recen >>= 1;
recen += (cnt*8);
recen+=2; /* this is not in the spec, but matches
the factory output, and has less failure */
recen <<= (dimm/2) * 8;
- if(!(dimm&1)) {
+ if (!(dimm&1)) {
recena |= recen;
}
else {
@@ -851,58 +851,58 @@ static void set_receive_enable(const struct mem_controller *ctrl)
}
}
/* Check for Eratta problem */
- for(i=cnt=0;i<32;i+=8) {
+ for (i=cnt=0;i<32;i+=8) {
if (((recena>>i)&0x0f)>7) {
cnt+= 0x101;
}
else {
- if((recena>>i)&0x0f) {
+ if ((recena>>i)&0x0f) {
cnt++;
}
}
}
- if(cnt&0x0f00) {
+ if (cnt&0x0f00) {
cnt = (cnt&0x0f) - (cnt>>16);
- if(cnt>1) {
- for(i=0;i<32;i+=8) {
- if(((recena>>i)&0x0f)>7) {
+ if (cnt>1) {
+ for (i=0;i<32;i+=8) {
+ if (((recena>>i)&0x0f)>7) {
recena &= ~(0x0f<<i);
recena |= (7<<i);
}
}
}
else {
- for(i=0;i<32;i+=8) {
- if(((recena>>i)&0x0f)<8) {
+ for (i=0;i<32;i+=8) {
+ if (((recena>>i)&0x0f)<8) {
recena &= ~(0x0f<<i);
recena |= (8<<i);
}
}
}
}
- for(i=cnt=0;i<32;i+=8) {
+ for (i=cnt=0;i<32;i+=8) {
if (((recenb>>i)&0x0f)>7) {
cnt+= 0x101;
}
else {
- if((recenb>>i)&0x0f) {
+ if ((recenb>>i)&0x0f) {
cnt++;
}
}
}
- if(cnt & 0x0f00) {
+ if (cnt & 0x0f00) {
cnt = (cnt&0x0f) - (cnt>>16);
- if(cnt>1) {
- for(i=0;i<32;i+=8) {
- if(((recenb>>i)&0x0f)>7) {
+ if (cnt>1) {
+ for (i=0;i<32;i+=8) {
+ if (((recenb>>i)&0x0f)>7) {
recenb &= ~(0x0f<<i);
recenb |= (7<<i);
}
}
}
else {
- for(i=0;i<32;i+=8) {
- if(((recenb>>8)&0x0f)<8) {
+ for (i=0;i<32;i+=8) {
+ if (((recenb>>8)&0x0f)<8) {
recenb &= ~(0x0f<<i);
recenb |= (8<<i);
}
@@ -978,7 +978,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
0x00410000 | CONFIG_DIMM_MAP_LOGICAL);
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
- if( drc == 0) {
+ if ( drc == 0) {
die("Error calculating DRC\n");
}
data32 = drc & ~(3 << 20); /* clear ECC mode */
@@ -986,7 +986,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
data32 = data32 | (1 << 5); /* temp turn off ODT */
/* Set gearing, then dram controller mode */
/* drc bits 3:2 = FSB speed */
- for(iptr = gearing[(drc>>2)&3].clkgr,cnt=0;cnt<4;cnt++) {
+ for (iptr = gearing[(drc>>2)&3].clkgr,cnt=0;cnt<4;cnt++) {
pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]);
}
/* 0x7c DRC */
@@ -1011,7 +1011,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* program DRT timing values */
cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
- for(i=0;i<8;i+=2) { /* loop through each dimm to test */
+ for (i=0;i<8;i+=2) { /* loop through each dimm to test */
printk(BIOS_DEBUG, "DIMM %08x\n", i);
/* Apply NOP */
do_delay();
@@ -1020,115 +1020,115 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));
do data32 = read32(MCBAR+DCALCSR);
- while(data32 & 0x80000000);
+ while (data32 & 0x80000000);
}
/* Apply NOP */
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));
do data32 = read32(MCBAR+DCALCSR);
- while(data32 & 0x80000000);
+ while (data32 & 0x80000000);
}
/* Precharg all banks */
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALADDR, 0x04000000);
write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
do data32 = read32(MCBAR+DCALCSR);
- while(data32 & 0x80000000);
+ while (data32 & 0x80000000);
}
/* EMRS dll's enabled */
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
/* fixme hard code AL additive latency */
write32(MCBAR+DCALADDR, 0x0b940001);
write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
do data32 = read32(MCBAR+DCALCSR);
- while(data32 & 0x80000000);
+ while (data32 & 0x80000000);
}
/* MRS reset dll's */
do_delay();
- if(cas_latency == 30)
+ if (cas_latency == 30)
mode_reg = 0x053a0000;
else
mode_reg = 0x054a0000;
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALADDR, mode_reg);
write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
do data32 = read32(MCBAR+DCALCSR);
- while(data32 & 0x80000000);
+ while (data32 & 0x80000000);
}
/* Precharg all banks */
do_delay();
do_delay();
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALADDR, 0x04000000);
write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
do data32 = read32(MCBAR+DCALCSR);
- while(data32 & 0x80000000);
+ while (data32 & 0x80000000);
}
/* Do 2 refreshes */
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
do data32 = read32(MCBAR+DCALCSR);
- while(data32 & 0x80000000);
+ while (data32 & 0x80000000);
}
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
do data32 = read32(MCBAR+DCALCSR);
- while(data32 & 0x80000000);
+ while (data32 & 0x80000000);
}
do_delay();
/* for good luck do 6 more */
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
}
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
}
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
}
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
}
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
}
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
}
do_delay();
/* MRS reset dll's normal */
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));
write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
do data32 = read32(MCBAR+DCALCSR);
- while(data32 & 0x80000000);
+ while (data32 & 0x80000000);
}
/* Do only if DDR2 EMRS dll's enabled */
do_delay();
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALADDR, (0x0b940001));
write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
do data32 = read32(MCBAR+DCALCSR);
- while(data32 & 0x80000000);
+ while (data32 & 0x80000000);
}
do_delay();
@@ -1143,7 +1143,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* DQS */
pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
- for(i = 0, cntptr = (MCBAR+0x200); i < 24; i++, cnt+=4) {
+ for (i = 0, cntptr = (MCBAR+0x200); i < 24; i++, cnt+=4) {
write32(cntptr, dqs_data[i]);
}
pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
@@ -1156,14 +1156,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* clear memory and init ECC */
printk(BIOS_DEBUG, "Clearing memory\n");
- for(i=0;i<64;i+=4) {
+ for (i=0;i<64;i+=4) {
write32(MCBAR+DCALDATA+i, 0x00000000);
}
- for(cs=0;cs<8;cs+=2) {
+ for (cs=0;cs<8;cs+=2) {
write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));
do data32 = read32(MCBAR+DCALCSR);
- while(data32 & 0x80000000);
+ while (data32 & 0x80000000);
}
/* Bring memory subsystem on line */
@@ -1172,9 +1172,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
pci_write_config32(ctrl->f0, 0x98, data32);
/* wait for completion */
printk(BIOS_DEBUG, "Waiting for mem complete\n");
- while(1) {
+ while (1) {
data32 = pci_read_config32(ctrl->f0, 0x98);
- if( (data32 & (1<<31)) == 0)
+ if ( (data32 & (1<<31)) == 0)
break;
}
printk(BIOS_DEBUG, "Done\n");
diff --git a/src/northbridge/intel/i3100/reset_test.c b/src/northbridge/intel/i3100/reset_test.c
index de86f8024d..1ea62c0a6c 100644
--- a/src/northbridge/intel/i3100/reset_test.c
+++ b/src/northbridge/intel/i3100/reset_test.c
@@ -12,7 +12,7 @@ int bios_reset_detected(void)
dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
- if( (dword & DRC_DONE) != 0 ) {
+ if ( (dword & DRC_DONE) != 0 ) {
return 1;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 06:31:42 +0000