diff options
Diffstat (limited to 'src/northbridge/intel/i3100')
| -rw-r--r-- | src/northbridge/intel/i3100/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i3100/pciexp_porta.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/i3100/pciexp_porta_ep80579.c | 8 |
3 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 0a04faf61a..195790f8cd 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -86,7 +86,7 @@ static void pci_domain_set_resources(device_t dev) pci_tolm = find_pci_tolm(&dev->link[0]); #if 1 - printk_debug("PCI mem marker = %x\n", pci_tolm); + printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); #endif /* FIXME Me temporary hack */ if(pci_tolm > 0xe0000000) diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c index b94094ed17..df375ee5f7 100644 --- a/src/northbridge/intel/i3100/pciexp_porta.c +++ b/src/northbridge/intel/i3100/pciexp_porta.c @@ -52,12 +52,12 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) int flag = 0; do { val = pci_read_config16(dev, 0x76); - printk_debug("pcie porta 0x76: %02x\n", val); + printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); if ((val & (1<<10)) && (!flag)) { /* training error */ ctl = pci_read_config16(dev, 0x74); pci_write_config16(dev, 0x74, (ctl | (1<<5))); val = pci_read_config16(dev, 0x76); - printk_debug("pcie porta reset 0x76: %02x\n", val); + printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); flag=1; hard_reset(); } diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index d51227c0aa..aff287cb56 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -44,7 +44,7 @@ static void pcie_init(struct device *dev) pci_write_config32(dev, 0x3c, config->intrline); } - printk_spew("configure PCIe port as \"Slot Implemented\"\n"); + printk(BIOS_SPEW, "configure PCIe port as \"Slot Implemented\"\n"); val = pci_read_config16(dev, 0x66); val &= ~(1<<8); val |= 1<<8; @@ -58,7 +58,7 @@ static void pcie_bus_enable_resources(struct device *dev) { u8 val8; if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk_spew("Enable VGA IO/MEM forwarding on PCIe port\n"); + printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n"); pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8); dev->command |= PCI_COMMAND_IO; @@ -76,12 +76,12 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) int flag = 0; do { val = pci_read_config16(dev, 0x76); - printk_debug("pcie porta 0x76: %02x\n", val); + printk(BIOS_DEBUG, "pcie porta 0x76: %02x\n", val); if ((val & (1<<11)) && (!flag)) { /* training error */ ctl = pci_read_config16(dev, 0x74); pci_write_config16(dev, 0x74, (ctl | (1<<5))); val = pci_read_config16(dev, 0x76); - printk_debug("pcie porta reset 0x76: %02x\n", val); + printk(BIOS_DEBUG, "pcie porta reset 0x76: %02x\n", val); flag=1; hard_reset(); } |