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Diffstat (limited to 'src/northbridge/intel/i440bx')
-rw-r--r--src/northbridge/intel/i440bx/raminit.c14
1 files changed, 2 insertions, 12 deletions
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index d5c23cf165..0a864e864a 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -357,10 +357,7 @@ static const u8 register_values[] = {
* 1 = Enable
* 0 = Disable
*/
- /* Enable normal refresh and the gated clock. */
- // TODO: Only do this later?
- // PMCR, 0x00, 0x14,
- PMCR, 0x00, 0x00,
+ /* PMCR will be set later. */
/* Enable SCRR.SRRAEN and let BX choose the SRR. */
SCRR + 1, 0x00, 0x10,
@@ -985,13 +982,6 @@ static void sdram_set_spd_registers(void)
/* Setup DRAM buffer strength. */
set_dram_buffer_strength();
-
- /* TODO: Set PMCR? */
- // pci_write_config8(NB, PMCR, 0x14);
- pci_write_config8(NB, PMCR, 0x10);
-
- /* TODO: This is for EDO memory only. */
- pci_write_config8(NB, DRAMT, 0x03);
}
static void sdram_enable(void)
@@ -1030,7 +1020,7 @@ static void sdram_enable(void)
/* 6. Finally enable refresh. */
PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
- // pci_write_config8(NB, PMCR, 0x10);
+ pci_write_config8(NB, PMCR, 0x10);
spd_enable_refresh();
udelay(1);