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-rw-r--r--src/northbridge/intel/i82810/debug.c4
-rw-r--r--src/northbridge/intel/i82810/raminit.c6
-rw-r--r--src/northbridge/intel/i82810/raminit.h4
3 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index 87b039f5f5..5bddbb60a3 100644
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -8,8 +8,8 @@ static void dump_spd_registers(void)
device = DIMM_SPD_BASE + i;
if (device) {
int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
+ print_debug("dimm: ");
+ print_debug_hex8(i);
print_debug(".0: ");
print_debug_hex8(device);
for(j = 0; j < 256; j++) {
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index fbb64f6088..81148e313d 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -312,7 +312,7 @@ static void set_dram_buffer_strength(void)
SPD_NUM_DIMM_BANKS) > 1;
d1.ss = !d1.ds;
}
-
+
buff_sc = 0;
/* Tame the beast... */
@@ -350,7 +350,7 @@ static void set_dram_buffer_strength(void)
buff_sc |= 1 << 14;
if (!d0.size && d1.size)
buff_sc |= 1 << 15;
-
+
print_debug("BUFF_SC calculated to 0x");
print_debug_hex16(buff_sc);
print_debug("\n");
@@ -371,7 +371,7 @@ static void sdram_set_registers(void)
/* Ideally, this should be R/W for as many ranges as possible. */
pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff);
-
+
/* Set size for onboard-VGA framebuffer. */
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
reg8 &= 0x3f; /* Disable graphics (for now). */
diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h
index 5a06dd171d..8c558a5699 100644
--- a/src/northbridge/intel/i82810/raminit.h
+++ b/src/northbridge/intel/i82810/raminit.h
@@ -27,7 +27,7 @@
/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
#define DIMM_SPD_BASE 0x50
-/* The following table has been bumped over to this header to avoid clutter in
+/* The following table has been bumped over to this header to avoid clutter in
* raminit.c. It's used to translate the value read from SPD Byte 31 to a value
* the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most
* northbridges have some sort of simple calculation that can be done for this,
@@ -38,7 +38,7 @@
/* TODO: Find a better way of doing this. */
static const uint8_t translate_spd_to_i82810[] = {
- /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB
+ /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB
* side can't be either, at least for now.
*/
/* TODO: For above case, only use the other side if > 4MB, and get some