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Diffstat (limited to 'src/northbridge/intel/i82830')
-rw-r--r--src/northbridge/intel/i82830/raminit.c12
-rw-r--r--src/northbridge/intel/i82830/raminit.h3
2 files changed, 6 insertions, 9 deletions
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
index 8d75c42189..f96306e2d1 100644
--- a/src/northbridge/intel/i82830/raminit.c
+++ b/src/northbridge/intel/i82830/raminit.c
@@ -101,16 +101,16 @@ static void initialize_dimm_rows(void)
switch (row) {
case 0:
- device = DIMM_SPD_BASE;
+ device = DIMM0;
break;
case 1:
- device = DIMM_SPD_BASE;
+ device = DIMM0;
break;
case 2:
- device = DIMM_SPD_BASE + 1;
+ device = DIMM0 + 1;
break;
case 3:
- device = DIMM_SPD_BASE + 1;
+ device = DIMM0 + 1;
break;
}
@@ -224,7 +224,7 @@ static void set_dram_row_boundaries(void)
for (i = 0; i < DIMM_SOCKETS; i++) {
struct dimm_size sz;
unsigned device;
- device = DIMM_SPD_BASE + i;
+ device = DIMM0 + i;
drb1 = 0;
drb2 = 0;
@@ -316,7 +316,7 @@ static void set_dram_row_attributes(void)
for (i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
- device = DIMM_SPD_BASE + i;
+ device = DIMM0 + i;
/* First check if a DIMM is actually present. */
if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
diff --git a/src/northbridge/intel/i82830/raminit.h b/src/northbridge/intel/i82830/raminit.h
index 3b4bf5fb2e..f54409bf4e 100644
--- a/src/northbridge/intel/i82830/raminit.h
+++ b/src/northbridge/intel/i82830/raminit.h
@@ -27,7 +27,4 @@
/* The 82830 supports max. 2 dual-sided SO-DIMMs. */
#define DIMM_SOCKETS 2
-/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
-#define DIMM_SPD_BASE 0x50
-
#endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */