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-rw-r--r--src/northbridge/intel/i945/acpi/hostbridge.asl3
-rw-r--r--src/northbridge/intel/i945/northbridge.c18
2 files changed, 17 insertions, 4 deletions
diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl
index 5877b0e922..7b3917da97 100644
--- a/src/northbridge/intel/i945/acpi/hostbridge.asl
+++ b/src/northbridge/intel/i945/acpi/hostbridge.asl
@@ -228,6 +228,3 @@ Method (_CRS, 0, Serialized)
Return (MCRS)
}
-
-/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-#include "acpi/i945_pci_irqs.asl"
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index b8a225562b..d3539b86e6 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -117,6 +117,22 @@ static void pci_domain_set_resources(struct device *dev)
assign_resources(dev->link_list);
}
+static const char *northbridge_acpi_name(const struct device *dev)
+{
+ if (dev->path.type == DEVICE_PATH_DOMAIN)
+ return "PCI0";
+
+ if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0)
+ return NULL;
+
+ switch (dev->path.pci.devfn) {
+ case PCI_DEVFN(0, 0):
+ return "MCHC";
+ }
+
+ return NULL;
+}
+
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
* See e7525/northbridge.c for an example.
@@ -127,6 +143,7 @@ static struct device_operations pci_domain_ops = {
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
+ .acpi_name = northbridge_acpi_name,
};
static void mc_read_resources(struct device *dev)
@@ -154,7 +171,6 @@ static void intel_set_subsystem(struct device *dev, unsigned int vendor,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
-
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
};