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Diffstat (limited to 'src/northbridge/intel/i945')
-rw-r--r--src/northbridge/intel/i945/bootblock.c1
-rw-r--r--src/northbridge/intel/i945/debug.c1
-rw-r--r--src/northbridge/intel/i945/northbridge.c1
-rw-r--r--src/northbridge/intel/i945/ram_calc.c1
-rw-r--r--src/northbridge/intel/i945/stage_cache.c1
5 files changed, 0 insertions, 5 deletions
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 1c00e8bebf..604088b1f3 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/
-#include <arch/io.h>
#include <device/pci_ops.h>
/* Just re-define this instead of including i945.h. It blows up romcc. */
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index 370131fb51..2acbc57f3c 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -15,7 +15,6 @@
*/
#include <spd.h>
-#include <arch/io.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 1dff3d14dd..ce7d292a27 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -15,7 +15,6 @@
#include <cbmem.h>
#include <console/console.h>
-#include <arch/io.h>
#include <device/pci_ops.h>
#include <stdint.h>
#include <device/device.h>
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index c797d42f09..124a6a8317 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -16,7 +16,6 @@
// Use simple device model for this file even in ramstage
#define __SIMPLE_DEVICE__
-#include <arch/io.h>
#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cbmem.h>
diff --git a/src/northbridge/intel/i945/stage_cache.c b/src/northbridge/intel/i945/stage_cache.c
index 26d4e7e5a6..b659796ea8 100644
--- a/src/northbridge/intel/i945/stage_cache.c
+++ b/src/northbridge/intel/i945/stage_cache.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <arch/io.h>
#include <cbmem.h>
#include <device/pci.h>
#include <stage_cache.h>