diff options
Diffstat (limited to 'src/northbridge/intel/pineview/ram_calc.c')
-rw-r--r-- | src/northbridge/intel/pineview/ram_calc.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index af1ca72dba..63f39428db 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -22,6 +22,8 @@ #include <console/console.h> #include <cbmem.h> #include <northbridge/intel/pineview/pineview.h> +#include <cpu/x86/mtrr.h> +#include <cpu/intel/romstage.h> u8 decode_pciebar(u32 *const base, u32 *const len) { @@ -91,3 +93,48 @@ u32 decode_igd_gtt_size(const u32 gsm) } return (u32)(gsmsize[gsm] << 10); } + +/* Depending of UMA and TSEG configuration, TSEG might start at any + * 1 MiB aligment. As this may cause very greedy MTRR setup, push + * CBMEM top downwards to 4 MiB boundary. + */ +void *cbmem_top(void) +{ + uintptr_t top_of_ram = pci_read_config32(PCI_DEV(0, 0, 0), TSEG); + top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB); + return (void *) top_of_ram; +} + +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +void *setup_stack_and_mtrrs(void) +{ + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache two separate 4 MiB regions below the top of ram, this + * satisfies MTRR alignment requirements. If you modify this to + * cover TSEG, make sure UMA region is not set with WRBACK as it + * causes hard-to-recover boot failures. + */ + top_of_ram = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); +} |