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-rw-r--r--src/northbridge/intel/pineview/Makefile.inc3
-rw-r--r--src/northbridge/intel/pineview/ram_calc.c13
-rw-r--r--src/northbridge/intel/pineview/stage_cache.c29
3 files changed, 13 insertions, 32 deletions
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
index 2d166138b6..83487717df 100644
--- a/src/northbridge/intel/pineview/Makefile.inc
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -30,8 +30,5 @@ romstage-y += raminit.c
romstage-y += early_init.c
postcar-y += ram_calc.c
-romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
-postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
endif
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index d1b43aa42d..a3caaf713a 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -26,6 +26,8 @@
#include <cpu/x86/mtrr.h>
#include <cpu/intel/romstage.h>
#include <cpu/intel/smm/gen1/smi.h>
+#include <stdint.h>
+#include <stage_cache.h>
u8 decode_pciebar(u32 *const base, u32 *const len)
{
@@ -138,6 +140,17 @@ void *cbmem_top(void)
}
+void stage_cache_external_region(void **base, size_t *size)
+{
+ /*
+ * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+ * The top of RAM is defined to be the TSEG base address.
+ */
+ *size = CONFIG_SMM_RESERVED_SIZE;
+ *base = (void *)(northbridge_get_tseg_base()
+ + CONFIG_SMM_RESERVED_SIZE);
+}
+
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
diff --git a/src/northbridge/intel/pineview/stage_cache.c b/src/northbridge/intel/pineview/stage_cache.c
deleted file mode 100644
index 47f08c1397..0000000000
--- a/src/northbridge/intel/pineview/stage_cache.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stage_cache.h>
-#include <cpu/intel/smm/gen1/smi.h>
-
-void stage_cache_external_region(void **base, size_t *size)
-{
- /*
- * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
- * The top of RAM is defined to be the TSEG base address.
- */
- *size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)(northbridge_get_tseg_base()
- + CONFIG_SMM_RESERVED_SIZE);
-}