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path: root/src/northbridge/intel/sandybridge/raminit.c
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Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit.c')
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index de6a542745..4ec8492b18 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -293,7 +293,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
int err;
u32 cpu;
- MCHBAR32(0x5f00) |= 1;
+ MCHBAR32(SAPMCTL) |= 1;
/* Wait for ME to be ready */
intel_early_me_init();
@@ -404,12 +404,12 @@ static void init_dram_ddr3(int min_tck, int s3resume)
if (err)
die("raminit failed");
- /* FIXME: should be hardware revision-dependent. */
- MCHBAR32(0x5024) = 0x00a030ce;
+ /* FIXME: should be hardware revision-dependent. The register only exists on IVB. */
+ MCHBAR32(CHANNEL_HASH) = 0x00a030ce;
set_scrambling_seed(&ctrl);
- set_42a0(&ctrl);
+ set_normal_operation(&ctrl);
final_registers(&ctrl);