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Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.h')
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index ab6e592f07..1f32dcddc4 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -94,6 +94,8 @@ typedef struct ramctr_timing_st {
u32 tWTR;
u32 tRTP;
u32 tFAW;
+ u32 tCWL;
+ u32 tCMD;
/* Latencies in terms of clock cycles
* They are saved separately as they are needed for DRAM MRS commands*/
u8 CAS; /* CAS read latency */