diff options
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_dmi.c | 168 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 20 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/finalize.c | 22 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/gma.c | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 64 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 312 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_iosav.c | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.c | 30 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_shared.c | 10 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 2 |
12 files changed, 320 insertions, 336 deletions
diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index 6f17cc1687..d9b7ed27ff 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -17,155 +17,155 @@ static void dmi_recipe(void) return; for (i = 0; i < 2; i++) { - DMIBAR32(0x0914 + (i << 5)) |= (1 << 31); + dmibar_setbits32(0x0914 + (i << 5), 1 << 31); } for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)) &= ~0x0c000000; - DMIBAR32(0x0a04 + (i << 4)) |= (1 << 11); + dmibar_clrbits32(0x0a00 + (i << 4), 3 << 26); + dmibar_setbits32(0x0a04 + (i << 4), 1 << 11); } - DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0x0fffffff) | (1 << 30); + dmibar_clrsetbits32(0x0c30, 0xf << 28, 1 << 30); for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)) &= ~0x01c00000; - DMIBAR32(0x090c + (i << 5)) &= ~0x000e0000; + dmibar_clrbits32(0x0904 + (i << 5), 7 << 22); + dmibar_clrbits32(0x090c + (i << 5), 7 << 17); } for (i = 0; i < 2; i++) { - DMIBAR32(0x090c + (i << 5)) &= ~0x01e00000; + dmibar_clrbits32(0x090c + (i << 5), 0xf << 21); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)); // !!! = 0x7a1842ec - DMIBAR32(0x0904 + (i << 5)) = 0x7a1842ec; - DMIBAR32(0x090c + (i << 5)); // !!! = 0x00000208 - DMIBAR32(0x090c + (i << 5)) = 0x00000128; + dmibar_read32(0x0904 + (i << 5)); // !!! = 0x7a1842ec + dmibar_write32(0x0904 + (i << 5), 0x7a1842ec); + dmibar_read32(0x090c + (i << 5)); // !!! = 0x00000208 + dmibar_write32(0x090c + (i << 5), 0x00000128); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 - DMIBAR32(0x0700 + (i << 5)) = 0x46139008; + dmibar_read32(0x0700 + (i << 5)); // !!! = 0x46139008 + dmibar_write32(0x0700 + (i << 5), 0x46139008); } - DMIBAR32(0x0c04); // !!! = 0x2e680008 - DMIBAR32(0x0c04) = 0x2e680008; + dmibar_read32(0x0c04); // !!! = 0x2e680008 + dmibar_write32(0x0c04, 0x2e680008); for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)); // !!! = 0x7a1842ec - DMIBAR32(0x0904 + (i << 5)) = 0x3a1842ec; + dmibar_read32(0x0904 + (i << 5)); // !!! = 0x7a1842ec + dmibar_write32(0x0904 + (i << 5), 0x3a1842ec); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0910 + (i << 5)); // !!! = 0x00006300 - DMIBAR32(0x0910 + (i << 5)) = 0x00004300; + dmibar_read32(0x0910 + (i << 5)); // !!! = 0x00006300 + dmibar_write32(0x0910 + (i << 5), 0x00004300); } for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042010 - DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + dmibar_read32(0x0a00 + (i << 4)); // !!! = 0x03042010 + dmibar_write32(0x0a00 + (i << 4), 0x03042018); } - DMIBAR32(0x0c00); // !!! = 0x29700c08 - DMIBAR32(0x0c00) = 0x29700c08; + dmibar_read32(0x0c00); // !!! = 0x29700c08 + dmibar_write32(0x0c00, 0x29700c08); for (i = 0; i < 4; i++) { - DMIBAR32(0x0a04 + (i << 4)); // !!! = 0x0c0708f0 - DMIBAR32(0x0a04 + (i << 4)) = 0x0c0718f0; + dmibar_read32(0x0a04 + (i << 4)); // !!! = 0x0c0708f0 + dmibar_write32(0x0a04 + (i << 4), 0x0c0718f0); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0900 + (i << 5)); // !!! = 0x50000000 - DMIBAR32(0x0900 + (i << 5)) = 0x50000000; + dmibar_read32(0x0900 + (i << 5)); // !!! = 0x50000000 + dmibar_write32(0x0900 + (i << 5), 0x50000000); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0908 + (i << 5)); // !!! = 0x51ffffff - DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff; + dmibar_read32(0x0908 + (i << 5)); // !!! = 0x51ffffff + dmibar_write32(0x0908 + (i << 5), 0x51ffffff); } for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 - DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + dmibar_read32(0x0a00 + (i << 4)); // !!! = 0x03042018 + dmibar_write32(0x0a00 + (i << 4), 0x03042018); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 - DMIBAR32(0x0700 + (i << 5)) = 0x46139008; + dmibar_read32(0x0700 + (i << 5)); // !!! = 0x46139008 + dmibar_write32(0x0700 + (i << 5), 0x46139008); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)); // !!! = 0x3a1842ec - DMIBAR32(0x0904 + (i << 5)) = 0x3a1846ec; + dmibar_read32(0x0904 + (i << 5)); // !!! = 0x3a1842ec + dmibar_write32(0x0904 + (i << 5), 0x3a1846ec); } for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 - DMIBAR32(0x0a00 + (i << 4)) = 0x03042018; + dmibar_read32(0x0a00 + (i << 4)); // !!! = 0x03042018 + dmibar_write32(0x0a00 + (i << 4), 0x03042018); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0908 + (i << 5)); // !!! = 0x51ffffff - DMIBAR32(0x0908 + (i << 5)) = 0x51ffffff; + dmibar_read32(0x0908 + (i << 5)); // !!! = 0x51ffffff + dmibar_write32(0x0908 + (i << 5), 0x51ffffff); } - DMIBAR32(0x0c00); // !!! = 0x29700c08 - DMIBAR32(0x0c00) = 0x29700c08; + dmibar_read32(0x0c00); // !!! = 0x29700c08 + dmibar_write32(0x0c00, 0x29700c08); - DMIBAR32(0x0c0c); // !!! = 0x16063400 - DMIBAR32(0x0c0c) = 0x00063400; + dmibar_read32(0x0c0c); // !!! = 0x16063400 + dmibar_write32(0x0c0c, 0x00063400); for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46139008 - DMIBAR32(0x0700 + (i << 5)) = 0x46339008; + dmibar_read32(0x0700 + (i << 5)); // !!! = 0x46139008 + dmibar_write32(0x0700 + (i << 5), 0x46339008); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x46339008 - DMIBAR32(0x0700 + (i << 5)) = 0x45339008; + dmibar_read32(0x0700 + (i << 5)); // !!! = 0x46339008 + dmibar_write32(0x0700 + (i << 5), 0x45339008); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x45339008 - DMIBAR32(0x0700 + (i << 5)) = 0x453b9008; + dmibar_read32(0x0700 + (i << 5)); // !!! = 0x45339008 + dmibar_write32(0x0700 + (i << 5), 0x453b9008); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x453b9008 - DMIBAR32(0x0700 + (i << 5)) = 0x45bb9008; + dmibar_read32(0x0700 + (i << 5)); // !!! = 0x453b9008 + dmibar_write32(0x0700 + (i << 5), 0x45bb9008); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0700 + (i << 5)); // !!! = 0x45bb9008 - DMIBAR32(0x0700 + (i << 5)) = 0x45fb9008; + dmibar_read32(0x0700 + (i << 5)); // !!! = 0x45bb9008 + dmibar_write32(0x0700 + (i << 5), 0x45fb9008); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9021a080 - DMIBAR32(0x0914 + (i << 5)) = 0x9021a280; + dmibar_read32(0x0914 + (i << 5)); // !!! = 0x9021a080 + dmibar_write32(0x0914 + (i << 5), 0x9021a280); } for (i = 0; i < 2; i++) { - DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9021a080 - DMIBAR32(0x0914 + (i << 5)) = 0x9821a280; + dmibar_read32(0x0914 + (i << 5)); // !!! = 0x9021a080 + dmibar_write32(0x0914 + (i << 5), 0x9821a280); } for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)); // !!! = 0x03042018 - DMIBAR32(0x0a00 + (i << 4)) = 0x03242018; + dmibar_read32(0x0a00 + (i << 4)); // !!! = 0x03042018 + dmibar_write32(0x0a00 + (i << 4), 0x03242018); } - DMIBAR32(0x0258); // !!! = 0x40000600 - DMIBAR32(0x0258) = 0x60000600; + dmibar_read32(0x0258); // !!! = 0x40000600 + dmibar_write32(0x0258, 0x60000600); for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)); // !!! = 0x3a1846ec - DMIBAR32(0x0904 + (i << 5)) = 0x2a1846ec; - DMIBAR32(0x0914 + (i << 5)); // !!! = 0x9821a280 - DMIBAR32(0x0914 + (i << 5)) = 0x98200280; + dmibar_read32(0x0904 + (i << 5)); // !!! = 0x3a1846ec + dmibar_write32(0x0904 + (i << 5), 0x2a1846ec); + dmibar_read32(0x0914 + (i << 5)); // !!! = 0x9821a280 + dmibar_write32(0x0914 + (i << 5), 0x98200280); } - DMIBAR32(DMIL0SLAT); // !!! = 0x00c26460 - DMIBAR32(DMIL0SLAT) = 0x00c2403c; + dmibar_read32(DMIL0SLAT); // !!! = 0x00c26460 + dmibar_write32(DMIL0SLAT, 0x00c2403c); } void early_init_dmi(void) @@ -175,21 +175,21 @@ void early_init_dmi(void) early_pch_init_native_dmi_pre(); /* Write once settings */ - DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) | + dmibar_clrsetbits32(DMILCAP, 0x3f00f, (2 << 0) | // 5GT/s (2 << 12) | // L0s 128 ns to less than 256 ns - (2 << 15); // L1 2 us to less than 4 us + (2 << 15)); // L1 2 us to less than 4 us - DMIBAR8(DMILCTL) |= (1 << 5); // Retrain link - while (DMIBAR16(DMILSTS) & TXTRN) + dmibar_setbits8(DMILCTL, 1 << 5); // Retrain link + while (dmibar_read16(DMILSTS) & TXTRN) ; - DMIBAR8(DMILCTL) |= (1 << 5); // Retrain link - while (DMIBAR16(DMILSTS) & TXTRN) + dmibar_setbits8(DMILCTL, 1 << 5); // Retrain link + while (dmibar_read16(DMILSTS) & TXTRN) ; - const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; - const u16 t = (DMIBAR16(DMILSTS) & 0x0f) * 2500; + const u8 w = (dmibar_read16(DMILSTS) >> 4) & 0x1f; + const u16 t = (dmibar_read16(DMILSTS) & 0x0f) * 2500; printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); /* @@ -201,16 +201,16 @@ void early_init_dmi(void) */ /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ - DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + dmibar_write32(DMIVC0RCTL, 1 << 31 | 0 << 24 | 0x0c << 1 | 1); /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ - DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); + dmibar_write32(DMIVC1RCTL, 1 << 31 | 1 << 24 | 0x11 << 1); /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ - DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); + dmibar_write32(DMIVCPRCTL, 1 << 31 | 2 << 24 | 0x22 << 1); /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ - DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); + dmibar_write32(DMIVCMRCTL, 1 << 31 | 7 << 24 | 0x40 << 1); /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ - DMIBAR8(DMIPVCCAP1) |= 1; + dmibar_setbits8(DMIPVCCAP1, 1 << 0); early_pch_init_native_dmi_post(); @@ -218,12 +218,12 @@ void early_init_dmi(void) * BIOS Requirement: Check if DMI VC Negotiation was successful. * Wait for virtual channels negotiation pending. */ - while (DMIBAR16(DMIVC0RSTS) & VC0NP) + while (dmibar_read16(DMIVC0RSTS) & VC0NP) ; - while (DMIBAR16(DMIVC1RSTS) & VC1NP) + while (dmibar_read16(DMIVC1RSTS) & VC1NP) ; - while (DMIBAR16(DMIVCPRSTS) & VCPNP) + while (dmibar_read16(DMIVCPRSTS) & VCPNP) ; - while (DMIBAR16(DMIVCMRSTS) & VCMNP) + while (dmibar_read16(DMIVCMRSTS) & VCMNP) ; } diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index b7ee3225ec..922c4b76f6 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -17,10 +17,10 @@ static void systemagent_vtd_init(void) return; /* Setup BARs */ - MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE >> 32; - MCHBAR32(GFXVTBAR) = GFXVT_BASE | 1; - MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE >> 32; - MCHBAR32(VTVC0BAR) = VTVC0_BASE | 1; + mchbar_write32(GFXVTBAR + 4, GFXVT_BASE >> 32); + mchbar_write32(GFXVTBAR + 0, GFXVT_BASE | 1); + mchbar_write32(VTVC0BAR + 4, VTVC0_BASE >> 32); + mchbar_write32(VTVC0BAR + 0, VTVC0_BASE | 1); /* Lock policies */ write32((void *)(GFXVT_BASE + 0xff0), 0x80000000); @@ -104,18 +104,18 @@ static void sandybridge_setup_graphics(void) pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); /* Erratum workarounds */ - MCHBAR32_OR(SAPMCTL, (1 << 9) | (1 << 10)); + mchbar_setbits32(SAPMCTL, 1 << 9 | 1 << 10); /* Enable SA Clock Gating */ - MCHBAR32_OR(SAPMCTL, 1); + mchbar_setbits32(SAPMCTL, 1 << 0); /* GPU RC6 workaround for sighting 366252 */ - MCHBAR32_OR(SSKPD_HI, 1 << 31); + mchbar_setbits32(SSKPD_HI, 1 << 31); /* VLW (Virtual Legacy Wire?) */ - MCHBAR32_AND(0x6120, ~(1 << 0)); + mchbar_clrbits32(0x6120, 1 << 0); - MCHBAR32_OR(INTRDIRCTL, (1 << 4) | (1 << 5)); + mchbar_setbits32(INTRDIRCTL, 1 << 4 | 1 << 5); } static void start_peg_link_training(void) @@ -195,5 +195,5 @@ void systemagent_early_init(void) void northbridge_romstage_finalize(void) { - MCHBAR16(SSKPD_HI) = 0xCAFE; + mchbar_write16(SSKPD_HI, 0xcafe); } diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 26c53060c9..96bfb37afd 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -18,19 +18,19 @@ void intel_sandybridge_finalize_smm(void) pci_or_config32(HOST_BRIDGE, TSEGMB, 1 << 0); pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); - MCHBAR32_OR(PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1 << 31); - MCHBAR32_OR(DMIVCLIM, 1 << 31); - MCHBAR32_OR(CRDTLCK, 1 << 0); + mchbar_setbits32(PAVP_MSG, 1 << 0); /* PAVP */ + mchbar_setbits32(SAPMCTL, 1 << 31); /* SA PM */ + mchbar_setbits32(UMAGFXCTL, 1 << 0); /* UMA GFX */ + mchbar_setbits32(VTDTRKLCK, 1 << 0); /* VTDTRK */ + mchbar_setbits32(REQLIM, 1 << 31); + mchbar_setbits32(DMIVCLIM, 1 << 31); + mchbar_setbits32(CRDTLCK, 1 << 0); /* Memory Controller Lockdown */ - MCHBAR8(MC_LOCK) = 0x8f; + mchbar_write8(MC_LOCK, 0x8f); /* Read+write the following */ - MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); - MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); - MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID); + mchbar_setbits32(VDMBDFBARKVM, 0); + mchbar_setbits32(VDMBDFBARPAVP, 0); + mchbar_setbits32(HDAUDRID, 0); } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 1e5458d4ab..38adbceae5 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -347,7 +347,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_write_powermeter(snb_pm_gt2); } } else { - u32 unit = MCHBAR32(0x5938) & 0xf; + u32 unit = mchbar_read32(0x5938) & 0xf; if (reg32 & (1 << 13)) { /* GT1 SKU */ @@ -355,7 +355,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) gtt_write_powermeter(ivb_pm_gt1); } else { /* GT2 SKU */ - u32 tdp = MCHBAR32(0x5930) & 0x7fff; + u32 tdp = mchbar_read32(0x5930) & 0x7fff; tdp /= (1 << unit); if (tdp <= 17) { @@ -467,7 +467,7 @@ static void gma_pm_init_pre_vbios(struct device *dev) /* 12: Normal Frequency Request */ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ /* only the lower 7 bits are used and shifted left by 25 */ - reg32 = MCHBAR32(0x5998); + reg32 = mchbar_read32(0x5998); reg32 >>= 16; reg32 &= 0x7f; reg32 <<= 25; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index fbed687f60..6e954611e1 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -214,56 +214,40 @@ static void northbridge_dmi_init(struct device *dev) /* Steps prior to DMI ASPM */ if (is_sandy) { - reg32 = DMIBAR32(0x250); - reg32 &= ~(7 << 20); - reg32 |= (2 << 20); - DMIBAR32(0x250) = reg32; + dmibar_clrsetbits32(0x250, 7 << 20, 2 << 20); } - reg32 = DMIBAR32(DMILLTC); - reg32 |= (1 << 29); - DMIBAR32(DMILLTC) = reg32; + dmibar_setbits32(DMILLTC, 1 << 29); if (is_sandy && stepping == SNB_STEP_C0) { - reg32 = DMIBAR32(0xbc8); - reg32 &= ~(0xfff << 7); - reg32 |= (0x7d3 << 7); - DMIBAR32(0xbc8) = reg32; + dmibar_clrsetbits32(0xbc8, 0xfff << 7, 0x7d3 << 7); } if (!is_sandy || stepping >= SNB_STEP_D1) { - reg32 = DMIBAR32(0x1f8); + reg32 = dmibar_read32(0x1f8); reg32 &= ~(1 << 26); reg32 |= (1 << 16); - DMIBAR32(0x1f8) = reg32; + dmibar_write32(0x1f8, reg32); - reg32 = DMIBAR32(0x1fc); - reg32 |= (1 << 12) | (1 << 23); - DMIBAR32(0x1fc) = reg32; + dmibar_setbits32(0x1fc, 1 << 12 | 1 << 23); } else if (stepping >= SNB_STEP_D0) { - reg32 = DMIBAR32(0x1f8); - reg32 |= (1 << 16); - DMIBAR32(0x1f8) = reg32; + dmibar_setbits32(0x1f8, 1 << 16); } /* Clear error status bits */ - DMIBAR32(DMIUESTS) = 0xffffffff; - DMIBAR32(DMICESTS) = 0xffffffff; + dmibar_write32(DMIUESTS, 0xffffffff); + dmibar_write32(DMICESTS, 0xffffffff); if (!is_sandy) - DMIBAR32(0xc34) = 0xffffffff; + dmibar_write32(0xc34, 0xffffffff); /* Enable ASPM on SNB link, should happen before PCH link */ if (is_sandy) { - reg32 = DMIBAR32(0xd04); - reg32 |= (1 << 4); - DMIBAR32(0xd04) = reg32; + dmibar_setbits32(0xd04, 1 << 4); } - reg32 = DMIBAR32(DMILCTL); - reg32 |= (1 << 1) | (1 << 0); - DMIBAR32(DMILCTL) = reg32; + dmibar_setbits32(DMILCTL, 1 << 1 | 1 << 0); } /* Disable unused PEG devices based on devicetree */ @@ -320,21 +304,20 @@ static void disable_peg(void) * * FIXME: Never clock gate on Ivy Bridge stepping A0! */ - MCHBAR32_OR(PEGCTL, 1); + mchbar_setbits32(PEGCTL, 1); printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); } else { - MCHBAR32_AND(PEGCTL, ~1); + mchbar_clrbits32(PEGCTL, 1); } } static void northbridge_init(struct device *dev) { - u8 bios_reset_cpl; u32 bridge_type; northbridge_dmi_init(dev); - bridge_type = MCHBAR32(SAPMTIMERS); + bridge_type = mchbar_read32(SAPMTIMERS); bridge_type &= ~0xff; if (is_sandybridge()) { @@ -342,15 +325,12 @@ static void northbridge_init(struct device *dev) bridge_type |= 0x20; } else { /* Enable Power Aware Interrupt Routing */ - u8 pair = MCHBAR8(INTRDIRCTL); - pair &= ~0x0f; /* Clear 3:0 */ - pair |= 0x04; /* Fixed Priority */ - MCHBAR8(INTRDIRCTL) = pair; + mchbar_clrsetbits8(INTRDIRCTL, 0xf, 0x4); /* Clear 3:0, set Fixed Priority */ /* 30h for IvyBridge */ bridge_type |= 0x30; } - MCHBAR32(SAPMTIMERS) = bridge_type; + mchbar_write32(SAPMTIMERS, bridge_type); /* Turn off unused devices. Has to be done before setting BIOS_RESET_CPL. */ disable_peg(); @@ -359,9 +339,7 @@ static void northbridge_init(struct device *dev) * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU * that BIOS has initialized memory and power management */ - bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); - bios_reset_cpl |= 1; - MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; + mchbar_setbits8(BIOS_RESET_CPL, 1 << 0); printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); /* Configure turbo power limits 1ms after reset complete bit */ @@ -374,12 +352,12 @@ static void northbridge_init(struct device *dev) */ if (cpu_config_tdp_levels()) { msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); - MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = msr.lo; - MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = msr.hi; + mchbar_write32(MCH_PKG_POWER_LIMIT_LO, msr.lo); + mchbar_write32(MCH_PKG_POWER_LIMIT_HI, msr.hi); } /* Set here before graphics PM init */ - MCHBAR32(PAVP_MSG) = 0x00100001; + mchbar_write32(PAVP_MSG, 0x00100001); } void northbridge_write_smram(u8 smram) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 92a0b720e2..a3e701686f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -300,7 +300,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) timestamp_add_now(TS_BEFORE_INITRAM); - MCHBAR32(SAPMCTL) |= 1; + mchbar_setbits32(SAPMCTL, 1 << 0); /* Wait for ME to be ready */ intel_early_me_init(); @@ -312,9 +312,9 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) wrmsr(0x2e6, (msr_t) { .lo = 0, .hi = 0 }); - const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000 + const u32 sskpd = mchbar_read32(SSKPD); // !!! = 0x00000000 if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) { - MCHBAR32(SSKPD) = 0; + mchbar_write32(SSKPD, 0); /* Need reset */ system_reset(); } @@ -413,7 +413,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) die("raminit failed"); /* FIXME: should be hardware revision-dependent. The register only exists on IVB. */ - MCHBAR32(CHANNEL_HASH) = 0x00a030ce; + mchbar_write32(CHANNEL_HASH, 0x00a030ce); set_scrambling_seed(&ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index c7273ad251..62a213961b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -26,10 +26,10 @@ static void sfence(void) /* Toggle IO reset bit */ static void toggle_io_reset(void) { - u32 r32 = MCHBAR32(MC_INIT_STATE_G); - MCHBAR32(MC_INIT_STATE_G) = r32 | (1 << 5); + u32 r32 = mchbar_read32(MC_INIT_STATE_G); + mchbar_write32(MC_INIT_STATE_G, r32 | (1 << 5)); udelay(1); - MCHBAR32(MC_INIT_STATE_G) = r32 & ~(1 << 5); + mchbar_write32(MC_INIT_STATE_G, r32 & ~(1 << 5)); udelay(1); } @@ -107,12 +107,12 @@ void dram_xover(ramctr_timing *ctrl) /* Enable xover clk */ reg = get_XOVER_CLK(ctrl->rankmap[channel]); printram("XOVER CLK [%x] = %x\n", GDCRCKPICODE_ch(channel), reg); - MCHBAR32(GDCRCKPICODE_ch(channel)) = reg; + mchbar_write32(GDCRCKPICODE_ch(channel), reg); /* Enable xover ctl & xover cmd */ reg = get_XOVER_CMD(ctrl->rankmap[channel]); printram("XOVER CMD [%x] = %x\n", GDCRCMDPICODING_ch(channel), reg); - MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg; + mchbar_write32(GDCRCMDPICODING_ch(channel), reg); } } @@ -130,17 +130,17 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel) stretch = 3; addr = SCHED_SECOND_CBIT_ch(channel); - MCHBAR32_AND_OR(addr, ~(0xf << 10), (stretch << 12) | (stretch << 10)); - printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); + mchbar_clrsetbits32(addr, 0xf << 10, stretch << 12 | stretch << 10); + printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, mchbar_read32(addr)); } else { addr = TC_OTHP_ch(channel); union tc_othp_reg tc_othp = { - .raw = MCHBAR32(addr), + .raw = mchbar_read32(addr), }; tc_othp.odt_delay_d0 = stretch; tc_othp.odt_delay_d1 = stretch; - MCHBAR32(addr) = tc_othp.raw; - printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); + mchbar_write32(addr, tc_othp.raw); + printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, mchbar_read32(addr)); } } @@ -210,32 +210,32 @@ void dram_timing_regs(ramctr_timing *ctrl) FOR_ALL_CHANNELS { printram("DBP [%x] = %x\n", TC_DBP_ch(channel), tc_dbp.raw); - MCHBAR32(TC_DBP_ch(channel)) = tc_dbp.raw; + mchbar_write32(TC_DBP_ch(channel), tc_dbp.raw); printram("RAP [%x] = %x\n", TC_RAP_ch(channel), tc_rap.raw); - MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; + mchbar_write32(TC_RAP_ch(channel), tc_rap.raw); printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), tc_othp.raw); - MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; + mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw); if (IS_IVY_CPU(ctrl->cpu)) { /* Debug parameters - only applies to Ivy Bridge */ - MCHBAR32(TC_DTP_ch(channel)) = tc_dtp.raw; + mchbar_write32(TC_DTP_ch(channel), tc_dtp.raw); } dram_odt_stretch(ctrl, channel); printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), tc_rftp.raw); - MCHBAR32(TC_RFTP_ch(channel)) = tc_rftp.raw; + mchbar_write32(TC_RFTP_ch(channel), tc_rftp.raw); union tc_rfp_reg tc_rfp = { - .raw = MCHBAR32(TC_RFP_ch(channel)), + .raw = mchbar_read32(TC_RFP_ch(channel)), }; tc_rfp.oref_ri = 0xff; - MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; + mchbar_write32(TC_RFP_ch(channel), tc_rfp.raw); printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), tc_srftp.raw); - MCHBAR32(TC_SRFTP_ch(channel)) = tc_srftp.raw; + mchbar_write32(TC_SRFTP_ch(channel), tc_srftp.raw); } } @@ -298,7 +298,7 @@ void dram_dimm_set_mapping(ramctr_timing *ctrl, int training) ecc = 0; FOR_ALL_CHANNELS { - MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel] | ecc; + mchbar_write32(MAD_DIMM(channel), ctrl->mad_dimm[channel] | ecc); } if (ctrl->ecc_enabled) @@ -321,20 +321,20 @@ void dram_zones(ramctr_timing *ctrl, int training) } if (ch0size >= ch1size) { - reg = MCHBAR32(MAD_ZR); + reg = mchbar_read32(MAD_ZR); val = ch1size / 256; reg = (reg & ~0xff000000) | val << 24; reg = (reg & ~0x00ff0000) | (2 * val) << 16; - MCHBAR32(MAD_ZR) = reg; - MCHBAR32(MAD_CHNL) = 0x24; + mchbar_write32(MAD_ZR, reg); + mchbar_write32(MAD_CHNL, 0x24); } else { - reg = MCHBAR32(MAD_ZR); + reg = mchbar_read32(MAD_ZR); val = ch0size / 256; reg = (reg & ~0xff000000) | val << 24; reg = (reg & ~0x00ff0000) | (2 * val) << 16; - MCHBAR32(MAD_ZR) = reg; - MCHBAR32(MAD_CHNL) = 0x21; + mchbar_write32(MAD_ZR, reg); + mchbar_write32(MAD_CHNL, 0x21); } } @@ -541,33 +541,33 @@ void dram_jedecreset(ramctr_timing *ctrl) u32 reg; int channel; - while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) + while (!(mchbar_read32(RCOMP_TIMER) & (1 << 16))) ; do { - reg = MCHBAR32(IOSAV_STATUS_ch(0)); + reg = mchbar_read32(IOSAV_STATUS_ch(0)); } while ((reg & 0x14) == 0); /* Set state of memory controller */ reg = 0x112; - MCHBAR32(MC_INIT_STATE_G) = reg; - MCHBAR32(MC_INIT_STATE) = 0; + mchbar_write32(MC_INIT_STATE_G, reg); + mchbar_write32(MC_INIT_STATE, 0); reg |= 2; /* DDR reset */ - MCHBAR32(MC_INIT_STATE_G) = reg; + mchbar_write32(MC_INIT_STATE_G, reg); /* Assert DIMM reset signal */ - MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 1)); + mchbar_clrbits32(MC_INIT_STATE_G, 1 << 1); /* Wait 200us */ udelay(200); /* Deassert DIMM reset signal */ - MCHBAR32_OR(MC_INIT_STATE_G, 1 << 1); + mchbar_setbits32(MC_INIT_STATE_G, 1 << 1); /* Wait 500us */ udelay(500); /* Enable DCLK */ - MCHBAR32_OR(MC_INIT_STATE_G, 1 << 2); + mchbar_setbits32(MC_INIT_STATE_G, 1 << 2); /* XXX Wait 20ns */ udelay(1); @@ -575,13 +575,13 @@ void dram_jedecreset(ramctr_timing *ctrl) FOR_ALL_CHANNELS { /* Set valid rank CKE */ reg = ctrl->rankmap[channel]; - MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; + mchbar_write32(MC_INIT_STATE_ch(channel), reg); /* Wait 10ns for ranks to settle */ // udelay(0.01); reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); - MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; + mchbar_write32(MC_INIT_STATE_ch(channel), reg); /* Write reset using a NOP */ write_reset(ctrl); @@ -788,7 +788,7 @@ static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) write_mrreg(ctrl, channel, rank, 2, mr2reg); /* Program MR2 shadow */ - u32 reg32 = MCHBAR32(TC_MR2_SHADOW_ch(channel)); + u32 reg32 = mchbar_read32(TC_MR2_SHADOW_ch(channel)); reg32 &= 3 << 14 | 3 << 6; @@ -800,7 +800,7 @@ static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) if (ctrl->rank_mirror[channel][rank]) reg32 |= 1 << (rank / 2 + 14); - MCHBAR32(TC_MR2_SHADOW_ch(channel)) = reg32; + mchbar_write32(TC_MR2_SHADOW_ch(channel), reg32); } static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) @@ -881,10 +881,10 @@ void dram_mrscommands(ramctr_timing *ctrl) } /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); + mchbar_setbits32(MC_INIT_STATE_G, 1 << 3); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); + mchbar_clrbits32(SCHED_CBIT_ch(channel), 1 << 21); wait_for_iosav(channel); @@ -989,12 +989,12 @@ void program_timings(ramctr_timing *ctrl, int channel) cmd_pi_coding.ctl_logic_delay_d0 = ctl_delay[0] / QCLK_PI; cmd_pi_coding.ctl_logic_delay_d1 = ctl_delay[1] / QCLK_PI; - MCHBAR32(GDCRCMDPICODING_ch(channel)) = cmd_pi_coding.raw; + mchbar_write32(GDCRCMDPICODING_ch(channel), cmd_pi_coding.raw); - MCHBAR32(GDCRCKPICODE_ch(channel)) = clk_pi_coding; - MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = clk_logic_dly; + mchbar_write32(GDCRCKPICODE_ch(channel), clk_pi_coding); + mchbar_write32(GDCRCKLOGICDELAY_ch(channel), clk_logic_dly); - reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); + reg_io_latency = mchbar_read32(SC_IO_LATENCY_ch(channel)); reg_io_latency &= ~0xffff; reg_roundtrip_latency = 0; @@ -1015,7 +1015,8 @@ void program_timings(ramctr_timing *ctrl, int channel) .rcven_logic_delay = rcven / QCLK_PI, .rx_dqs_n_pi_code = dqs_n, }; - MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = gdcr_rx.raw; + mchbar_write32(lane_base[lane] + GDCRRX(channel, slotrank), + gdcr_rx.raw); const u16 tx_dqs = ctrl->timings[channel][slotrank].lanes[lane].tx_dqs; const int tx_dq = ctrl->timings[channel][slotrank].lanes[lane].tx_dq; @@ -1025,11 +1026,12 @@ void program_timings(ramctr_timing *ctrl, int channel) .tx_dqs_logic_delay = tx_dqs / QCLK_PI, .tx_dq_logic_delay = tx_dq / QCLK_PI, }; - MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = gdcr_tx.raw; + mchbar_write32(lane_base[lane] + GDCRTX(channel, slotrank), + gdcr_tx.raw); } } - MCHBAR32(SC_ROUNDT_LAT_ch(channel)) = reg_roundtrip_latency; - MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; + mchbar_write32(SC_ROUNDT_LAT_ch(channel), reg_roundtrip_latency); + mchbar_write32(SC_IO_LATENCY_ch(channel), reg_io_latency); } static void test_rcven(ramctr_timing *ctrl, int channel, int slotrank) @@ -1046,7 +1048,7 @@ static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int la { u32 rcven = ctrl->timings[channel][slotrank].lanes[lane].rcven; - return (MCHBAR32(lane_base[lane] + + return (mchbar_read32(lane_base[lane] + GDCRTRAININGRESULT(channel, (rcven / 32) & 1)) >> (rcven % 32)) & 1; } @@ -1328,7 +1330,7 @@ int receive_enable_calibration(ramctr_timing *ctrl) .training_rank_sel = slotrank, .odt_always_on = 1, }; - MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; + mchbar_write32(GDCRTRAININGMOD, training_mod.raw); ctrl->timings[channel][slotrank].io_latency = 4; ctrl->timings[channel][slotrank].roundtrip_latency = 55; @@ -1387,7 +1389,7 @@ int receive_enable_calibration(ramctr_timing *ctrl) printram("Aval: %d, %d, %d: % 4d\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].rcven); - MCHBAR32(GDCRTRAININGMOD) = 0; + mchbar_write32(GDCRTRAININGMOD, 0); toggle_io_reset(); } @@ -1404,8 +1406,8 @@ static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank) int lane; FOR_ALL_LANES { - MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; - MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); + mchbar_write32(IOSAV_By_ERROR_COUNT_ch(channel, lane), 0); + mchbar_read32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); } wait_for_iosav(channel); @@ -1458,7 +1460,8 @@ static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) test_tx_dq(ctrl, channel, slotrank); FOR_ALL_LANES { - stats[lane][tx_dq] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + stats[lane][tx_dq] = mchbar_read32( + IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } FOR_ALL_LANES { @@ -1499,7 +1502,7 @@ static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) /* Each cacheline is 64 bits long */ static void program_wdb_pattern_length(int channel, const unsigned int num_cachelines) { - MCHBAR8(IOSAV_DATA_CTL_ch(channel)) = num_cachelines / 8 - 1; + mchbar_write8(IOSAV_DATA_CTL_ch(channel), num_cachelines / 8 - 1); } static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) @@ -1555,7 +1558,7 @@ static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank) .odt_always_on = 1, .force_drive_enable = 1, }; - MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; + mchbar_write32(GDCRTRAININGMOD, training_mod.raw); u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; int bank = 1; @@ -1576,7 +1579,7 @@ static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank) iosav_run_once_and_wait(channel); FOR_ALL_LANES { - statistics[lane][tx_dqs] = !((MCHBAR32(lane_base[lane] + + statistics[lane][tx_dqs] = !((mchbar_read32(lane_base[lane] + GDCRTRAININGRESULT(channel, (tx_dqs / 32) & 1)) >> (tx_dqs % 32)) & 1); } @@ -1637,7 +1640,7 @@ static void train_write_flyby(ramctr_timing *ctrl) const union gdcr_training_mod_reg training_mod = { .dq_dqs_training_res = 1, }; - MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; + mchbar_write32(GDCRTRAININGMOD, training_mod.raw); FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); @@ -1645,7 +1648,7 @@ static void train_write_flyby(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { /* Reset read and write WDB pointers */ - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x10001; + mchbar_write32(IOSAV_DATA_CTL_ch(channel), 0x10001); wait_for_iosav(channel); @@ -1722,8 +1725,8 @@ static void train_write_flyby(ramctr_timing *ctrl) iosav_run_once_and_wait(channel); FOR_ALL_LANES { - u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); - res |= ((u64) MCHBAR32(lane_base[lane] + + u64 res = mchbar_read32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); + res |= ((u64) mchbar_read32(lane_base[lane] + GDCRTRAININGRESULT2(channel))) << 32; old = ctrl->timings[channel][slotrank].lanes[lane].tx_dqs; @@ -1735,7 +1738,7 @@ static void train_write_flyby(ramctr_timing *ctrl) old, ctrl->timings[channel][slotrank].lanes[lane].tx_dqs); } } - MCHBAR32(GDCRTRAININGMOD) = 0; + mchbar_write32(GDCRTRAININGMOD, 0); } static void disable_refresh_machine(ramctr_timing *ctrl) @@ -1750,11 +1753,11 @@ static void disable_refresh_machine(ramctr_timing *ctrl) iosav_run_once_and_wait(channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); + mchbar_setbits32(SCHED_CBIT_ch(channel), 1 << 21); } /* Refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); + mchbar_clrbits32(MC_INIT_STATE_G, 1 << 3); FOR_ALL_POPULATED_CHANNELS { /* Execute the same command queue */ @@ -1794,7 +1797,7 @@ static int jedec_write_leveling(ramctr_timing *ctrl) .odt_always_on = 1, .force_drive_enable = 1, }; - MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; + mchbar_write32(GDCRTRAININGMOD, training_mod.raw); toggle_io_reset(); @@ -1809,17 +1812,17 @@ static int jedec_write_leveling(ramctr_timing *ctrl) FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); - MCHBAR32(GDCRTRAININGMOD) = 0; + mchbar_write32(GDCRTRAININGMOD, 0); FOR_ALL_POPULATED_CHANNELS wait_for_iosav(channel); /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 1 << 3); + mchbar_setbits32(MC_INIT_STATE_G, 1 << 3); FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~(1 << 21)); - MCHBAR32(IOSAV_STATUS_ch(channel)); + mchbar_clrbits32(SCHED_CBIT_ch(channel), 1 << 21); + mchbar_read32(IOSAV_STATUS_ch(channel)); wait_for_iosav(channel); iosav_write_zqcs_sequence(channel, 0, 4, 101, 31); @@ -1842,7 +1845,7 @@ int write_training(ramctr_timing *ctrl) * Needs to be done before starting the write training procedure. */ FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); + mchbar_setbits32(TC_RWP_ch(channel), 1 << 27); printram("CPE\n"); @@ -1889,24 +1892,24 @@ static int test_command_training(ramctr_timing *ctrl, int channel, int slotrank) } program_timings(ctrl, channel); FOR_ALL_LANES { - MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; + mchbar_write32(IOSAV_By_ERROR_COUNT(lane), 0); } /* Reset read WDB pointer */ - MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; + mchbar_write32(IOSAV_DATA_CTL_ch(channel), 0x1f); wait_for_iosav(channel); iosav_write_command_training_sequence(ctrl, channel, slotrank, ctr); /* Program LFSR for the RD/WR subsequences */ - MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; - MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; + mchbar_write32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1), 0x389abcd); + mchbar_write32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2), 0x389abcd); iosav_run_once_and_wait(channel); FOR_ALL_LANES { - u32 r32 = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + u32 r32 = mchbar_read32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); if (r32 == 0) lanes_ok |= 1 << lane; @@ -1997,7 +2000,7 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) .tWR = ctrl->tWR, .tCMD = ctrl->cmd_stretch[channel], }; - MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; + mchbar_write32(TC_RAP_ch(channel), tc_rap.raw); if (ctrl->cmd_stretch[channel] == 2) delta = 2; @@ -2106,8 +2109,8 @@ static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, program_timings(ctrl, channel); FOR_ALL_LANES { - MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; - MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); + mchbar_write32(IOSAV_By_ERROR_COUNT_ch(channel, lane), 0); + mchbar_read32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); } wait_for_iosav(channel); @@ -2118,7 +2121,8 @@ static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, iosav_run_once_and_wait(channel); FOR_ALL_LANES { - stats[lane][dqs_pi] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + stats[lane][dqs_pi] = mchbar_read32( + IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } @@ -2142,8 +2146,8 @@ static void find_predefined_pattern(ramctr_timing *ctrl, const int channel) fill_pattern0(ctrl, channel, 0, 0); FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); + mchbar_write32(IOSAV_By_BW_MASK_ch(channel, lane), 0); + mchbar_read32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { @@ -2183,8 +2187,8 @@ static void find_predefined_pattern(ramctr_timing *ctrl, const int channel) /* XXX: check any measured value ? */ FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = - ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; + mchbar_write32(IOSAV_By_BW_MASK_ch(channel, lane), + ~mchbar_read32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff); } } @@ -2195,7 +2199,7 @@ int read_mpr_training(ramctr_timing *ctrl) int channel, slotrank, lane; int err; - MCHBAR32(GDCRTRAININGMOD) = 0; + mchbar_write32(GDCRTRAININGMOD, 0); toggle_io_reset(); @@ -2209,7 +2213,7 @@ int read_mpr_training(ramctr_timing *ctrl) * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will * also use a single loop. It would seem that it is a debugging configuration. */ - MCHBAR32(IOSAV_DC_MASK) = 3 << 8; + mchbar_write32(IOSAV_DC_MASK, 3 << 8); printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 3 << 8); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2219,7 +2223,7 @@ int read_mpr_training(ramctr_timing *ctrl) return err; } - MCHBAR32(IOSAV_DC_MASK) = 2 << 8; + mchbar_write32(IOSAV_DC_MASK, 2 << 8); printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 2 << 8); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2229,7 +2233,7 @@ int read_mpr_training(ramctr_timing *ctrl) return err; } - MCHBAR32(IOSAV_DC_MASK) = 0; + mchbar_write32(IOSAV_DC_MASK, 0); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = @@ -2243,7 +2247,7 @@ int read_mpr_training(ramctr_timing *ctrl) } FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; + mchbar_write32(IOSAV_By_BW_MASK_ch(channel, lane), 0); } return 0; } @@ -2266,7 +2270,7 @@ static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank const union gdcr_training_mod_reg training_mod = { .vref_gen_ctl = rd_vref_offsets[i], }; - MCHBAR32(GDCRTRAININGMOD_ch(channel)) = training_mod.raw; + mchbar_write32(GDCRTRAININGMOD_ch(channel), training_mod.raw); printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), training_mod.raw); for (pat = 0; pat < NUM_PATTERNS; pat++) { @@ -2283,8 +2287,9 @@ static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank program_timings(ctrl, channel); FOR_ALL_LANES { - MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; - MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); + mchbar_write32(IOSAV_By_ERROR_COUNT_ch(channel, lane), + 0); + mchbar_read32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); } wait_for_iosav(channel); @@ -2293,11 +2298,12 @@ static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank iosav_run_once_and_wait(channel); FOR_ALL_LANES { - MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + mchbar_read32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } /* FIXME: This register only exists on Ivy Bridge */ - raw_stats[read_pi] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); + raw_stats[read_pi] = mchbar_read32( + IOSAV_BYTE_SERROR_C_ch(channel)); } FOR_ALL_LANES { @@ -2329,7 +2335,7 @@ static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank } /* Restore nominal Vref after training */ - MCHBAR32(GDCRTRAININGMOD_ch(channel)) = 0; + mchbar_write32(GDCRTRAININGMOD_ch(channel), 0); printram("CPA\n"); return 0; } @@ -2344,7 +2350,7 @@ int aggressive_read_training(ramctr_timing *ctrl) * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will * also use a single loop. It would seem that it is a debugging configuration. */ - MCHBAR32(IOSAV_DC_MASK) = 3 << 8; + mchbar_write32(IOSAV_DC_MASK, 3 << 8); printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 3 << 8); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2354,7 +2360,7 @@ int aggressive_read_training(ramctr_timing *ctrl) return err; } - MCHBAR32(IOSAV_DC_MASK) = 2 << 8; + mchbar_write32(IOSAV_DC_MASK, 2 << 8); printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 2 << 8); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { @@ -2364,7 +2370,7 @@ int aggressive_read_training(ramctr_timing *ctrl) return err; } - MCHBAR32(IOSAV_DC_MASK) = 0; + mchbar_write32(IOSAV_DC_MASK, 0); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].rx_dqs_n = @@ -2391,7 +2397,7 @@ static void test_aggressive_write(ramctr_timing *ctrl, int channel, int slotrank static void set_write_vref(const int channel, const u8 wr_vref) { - MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~(0x3f << 24), wr_vref << 24); + mchbar_clrsetbits32(GDCRCMDDEBUGMUXCFG_Cz_S(channel), 0x3f << 24, wr_vref << 24); udelay(2); } @@ -2420,7 +2426,7 @@ int aggressive_write_training(ramctr_timing *ctrl) const bool enable_iosav_opt = IS_IVY_CPU_D(ctrl->cpu) || IS_IVY_CPU_E(ctrl->cpu); if (enable_iosav_opt) - MCHBAR32(MCMNTS_SPARE) = 1; + mchbar_write32(MCMNTS_SPARE, 1); printram("Aggresive write training:\n"); @@ -2448,7 +2454,7 @@ int aggressive_write_training(ramctr_timing *ctrl) test_aggressive_write(ctrl, channel, slotrank); - raw_stats[tx_dq] = MCHBAR32( + raw_stats[tx_dq] = mchbar_read32( IOSAV_BYTE_SERROR_C_ch(channel)); } FOR_ALL_LANES { @@ -2495,7 +2501,7 @@ int aggressive_write_training(ramctr_timing *ctrl) /* Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization */ if (enable_iosav_opt) - MCHBAR32(MCMNTS_SPARE) = 0; + mchbar_write32(MCMNTS_SPARE, 0); printram("CPB\n"); @@ -2546,7 +2552,7 @@ int channel_test(ramctr_timing *ctrl) slotrank = 0; FOR_ALL_POPULATED_CHANNELS - if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { + if (mchbar_read32(MC_INIT_STATE_ch(channel)) & 0xa000) { printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); return MAKE_ERR; } @@ -2558,8 +2564,8 @@ int channel_test(ramctr_timing *ctrl) FOR_ALL_CHANNELS if (ctrl->rankmap[channel] & (1 << slotrank)) { FOR_ALL_LANES { - MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; - MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; + mchbar_write32(IOSAV_By_ERROR_COUNT(lane), 0); + mchbar_write32(IOSAV_By_BW_SERROR_C(lane), 0); } wait_for_iosav(channel); @@ -2568,7 +2574,7 @@ int channel_test(ramctr_timing *ctrl) iosav_run_once_and_wait(channel); FOR_ALL_LANES - if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { + if (mchbar_read32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", channel, slotrank, lane); return MAKE_ERR; @@ -2704,19 +2710,19 @@ void set_scrambling_seed(ramctr_timing *ctrl) {0x00028bfa, 0x53fe4b49, 0x19ed5483} }; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(SCHED_CBIT_ch(channel)) &= ~(1 << 28); - MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; - MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1]; - MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2]; + mchbar_clrbits32(SCHED_CBIT_ch(channel), 1 << 28); + mchbar_write32(SCRAMBLING_SEED_1_ch(channel), seeds[channel][0]); + mchbar_write32(SCRAMBLING_SEED_2_HI_ch(channel), seeds[channel][1]); + mchbar_write32(SCRAMBLING_SEED_2_LO_ch(channel), seeds[channel][2]); } } void set_wmm_behavior(const u32 cpu) { if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { - MCHBAR32(SC_WDBWM) = 0x141d1519; + mchbar_write32(SC_WDBWM, 0x141d1519); } else { - MCHBAR32(SC_WDBWM) = 0x551d1519; + mchbar_write32(SC_WDBWM, 0x551d1519); } } @@ -2726,7 +2732,7 @@ void prepare_training(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS { /* Always drive command bus */ - MCHBAR32_OR(TC_RAP_ch(channel), 1 << 29); + mchbar_setbits32(TC_RAP_ch(channel), 1 << 29); } udelay(1); @@ -2768,7 +2774,7 @@ void set_read_write_timings(ramctr_timing *ctrl) .tRWSR = 2, .dec_wrd = 1, }; - MCHBAR32(TC_RWP_ch(channel)) = tc_rwp.raw; + mchbar_write32(TC_RWP_ch(channel), tc_rwp.raw); } } @@ -2776,8 +2782,8 @@ void set_normal_operation(ramctr_timing *ctrl) { int channel; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(MC_INIT_STATE_ch(channel)) = (1 << 12) | ctrl->rankmap[channel]; - MCHBAR32_AND(TC_RAP_ch(channel), ~(1 << 29)); + mchbar_write32(MC_INIT_STATE_ch(channel), 1 << 12 | ctrl->rankmap[channel]); + mchbar_clrbits32(TC_RAP_ch(channel), 1 << 29); } } @@ -2796,84 +2802,84 @@ void final_registers(ramctr_timing *ctrl) u32 r32; /* FIXME: This register only exists on Ivy Bridge */ - MCHBAR32(WMM_READ_CONFIG) = 0x46; + mchbar_write32(WMM_READ_CONFIG, 0x46); FOR_ALL_CHANNELS { union tc_othp_reg tc_othp = { - .raw = MCHBAR32(TC_OTHP_ch(channel)), + .raw = mchbar_read32(TC_OTHP_ch(channel)), }; tc_othp.tCPDED = 1; - MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; + mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw); } /* 64 DCLKs until idle, decision per rank */ - MCHBAR32(PM_PDWN_CONFIG) = get_power_down_mode(ctrl) << 8 | 64; + mchbar_write32(PM_PDWN_CONFIG, get_power_down_mode(ctrl) << 8 | 64); FOR_ALL_CHANNELS - MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; + mchbar_write32(PM_TRML_M_CONFIG_ch(channel), 0x00000aaa); - MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; - MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->mdll_wake_delay; + mchbar_write32(PM_BW_LIMIT_CONFIG, 0x5f7003ff); + mchbar_write32(PM_DLL_CONFIG, 0x00073000 | ctrl->mdll_wake_delay); FOR_ALL_CHANNELS { switch (ctrl->rankmap[channel]) { /* Unpopulated channel */ case 0: - MCHBAR32(PM_CMD_PWR_ch(channel)) = 0; + mchbar_write32(PM_CMD_PWR_ch(channel), 0); break; /* Only single-ranked dimms */ case 1: case 4: case 5: - MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x00373131; + mchbar_write32(PM_CMD_PWR_ch(channel), 0x00373131); break; /* Dual-ranked dimms present */ default: - MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x009b6ea1; + mchbar_write32(PM_CMD_PWR_ch(channel), 0x009b6ea1); break; } } - MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; - MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); - MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); + mchbar_write32(MEM_TRML_ESTIMATION_CONFIG, 0xca9171e5); + mchbar_clrsetbits32(MEM_TRML_THRESHOLDS_CONFIG, 0x00ffffff, 0x00e4d5d0); + mchbar_clrbits32(MEM_TRML_INTERRUPT, 0x1f); FOR_ALL_CHANNELS { union tc_rfp_reg tc_rfp = { - .raw = MCHBAR32(TC_RFP_ch(channel)), + .raw = mchbar_read32(TC_RFP_ch(channel)), }; tc_rfp.refresh_2x_control = 1; - MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; + mchbar_write32(TC_RFP_ch(channel), tc_rfp.raw); } - MCHBAR32_OR(MC_INIT_STATE_G, 1 << 0); - MCHBAR32_OR(MC_INIT_STATE_G, 1 << 7); - MCHBAR32(BANDTIMERS_SNB) = 0xfa; + mchbar_setbits32(MC_INIT_STATE_G, 1 << 0); + mchbar_setbits32(MC_INIT_STATE_G, 1 << 7); + mchbar_write32(BANDTIMERS_SNB, 0xfa); /* Find a populated channel */ FOR_ALL_POPULATED_CHANNELS break; - t1_cycles = (MCHBAR32(TC_ZQCAL_ch(channel)) >> 8) & 0xff; - r32 = MCHBAR32(PM_DLL_CONFIG); + t1_cycles = (mchbar_read32(TC_ZQCAL_ch(channel)) >> 8) & 0xff; + r32 = mchbar_read32(PM_DLL_CONFIG); if (r32 & (1 << 17)) t1_cycles += (r32 & 0xfff); - t1_cycles += MCHBAR32(TC_SRFTP_ch(channel)) & 0xfff; + t1_cycles += mchbar_read32(TC_SRFTP_ch(channel)) & 0xfff; t1_ns = t1_cycles * ctrl->tCK / 256 + 544; if (!(r32 & (1 << 17))) t1_ns += 500; - t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); - if (MCHBAR32(SAPMCTL) & 8) { - t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); - t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); + t2_ns = 10 * ((mchbar_read32(SAPMTIMERS) >> 8) & 0xfff); + if (mchbar_read32(SAPMCTL) & 8) { + t3_ns = 10 * ((mchbar_read32(BANDTIMERS_IVB) >> 8) & 0xfff); + t3_ns += 10 * (mchbar_read32(SAPMTIMERS2_IVB) & 0xff); } else { t3_ns = 500; } /* The graphics driver will use these watermark values */ printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - MCHBAR32_AND_OR(SSKPD, ~0x3f3f3f3f, + mchbar_clrsetbits32(SSKPD, 0x3f3f3f3f, ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); } @@ -2892,7 +2898,7 @@ void restore_timings(ramctr_timing *ctrl) .tWR = ctrl->tWR, .tCMD = ctrl->cmd_stretch[channel], }; - MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; + mchbar_write32(TC_RAP_ch(channel), tc_rap.raw); } udelay(1); @@ -2902,17 +2908,17 @@ void restore_timings(ramctr_timing *ctrl) } FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); + mchbar_setbits32(TC_RWP_ch(channel), 1 << 27); FOR_ALL_POPULATED_CHANNELS { udelay(1); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); + mchbar_setbits32(SCHED_CBIT_ch(channel), 1 << 21); } printram("CPE\n"); - MCHBAR32(GDCRTRAININGMOD) = 0; - MCHBAR32(IOSAV_DC_MASK) = 0; + mchbar_write32(GDCRTRAININGMOD, 0); + mchbar_write32(IOSAV_DC_MASK, 0); printram("CP5b\n"); @@ -2923,16 +2929,16 @@ void restore_timings(ramctr_timing *ctrl) u32 reg, addr; /* Poll for RCOMP */ - while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) + while (!(mchbar_read32(RCOMP_TIMER) & (1 << 16))) ; do { - reg = MCHBAR32(IOSAV_STATUS_ch(0)); + reg = mchbar_read32(IOSAV_STATUS_ch(0)); } while ((reg & 0x14) == 0); /* Set state of memory controller */ - MCHBAR32(MC_INIT_STATE_G) = 0x116; - MCHBAR32(MC_INIT_STATE) = 0; + mchbar_write32(MC_INIT_STATE_G, 0x116); + mchbar_write32(MC_INIT_STATE, 0); /* Wait 500us */ udelay(500); @@ -2942,13 +2948,13 @@ void restore_timings(ramctr_timing *ctrl) reg = 0; reg = (reg & ~0x0f) | ctrl->rankmap[channel]; addr = MC_INIT_STATE_ch(channel); - MCHBAR32(addr) = reg; + mchbar_write32(addr, reg); /* Wait 10ns for ranks to settle */ // udelay(0.01); reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); - MCHBAR32(addr) = reg; + mchbar_write32(addr, reg); /* Write reset using a NOP */ write_reset(ctrl); @@ -2959,10 +2965,10 @@ void restore_timings(ramctr_timing *ctrl) printram("CP5c\n"); - MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; + mchbar_write32(GDCRTRAININGMOD_ch(0), 0); FOR_ALL_CHANNELS { - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~(0x3f << 24)); + mchbar_clrbits32(GDCRCMDDEBUGMUXCFG_Cz_S(channel), 0x3f << 24); udelay(2); } } diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index b9533bafb7..e337c40e01 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -17,10 +17,10 @@ static unsigned int ssq_count = 0; void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length) { for (unsigned int i = 0; i < length; i++) { - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, i)) = seq[i].sp_cmd_ctrl.raw; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, i)) = seq[i].subseq_ctrl.raw; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, i)) = seq[i].sp_cmd_addr.raw; - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, i)) = seq[i].addr_update.raw; + mchbar_write32(IOSAV_n_SP_CMD_CTRL_ch(ch, i), seq[i].sp_cmd_ctrl.raw); + mchbar_write32(IOSAV_n_SUBSEQ_CTRL_ch(ch, i), seq[i].subseq_ctrl.raw); + mchbar_write32(IOSAV_n_SP_CMD_ADDR_ch(ch, i), seq[i].sp_cmd_addr.raw); + mchbar_write32(IOSAV_n_ADDR_UPDATE_ch(ch, i), seq[i].addr_update.raw); } ssq_count = length; @@ -32,13 +32,13 @@ void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer) if (ssq_count == 0) return; - MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22); + mchbar_write32(IOSAV_SEQ_CTL_ch(ch), loops | (ssq_count - 1) << 18 | as_timer << 22); } void wait_for_iosav(int channel) { while (1) { - if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) + if (mchbar_read32(IOSAV_STATUS_ch(channel)) & 0x50) return; } } diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 149860de05..21de0b2ea4 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -175,7 +175,7 @@ void sdram_initialize(struct pei_data *pei_data) usbdebug_hw_init(true); /* Print the MRC version after executing the UEFI PEI stage */ - u32 version = MCHBAR32(MRC_REVISION); + u32 version = mchbar_read32(MRC_REVISION); printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", (version >> 24) & 0xff, (version >> 16) & 0xff, (version >> 8) & 0xff, (version >> 0) & 0xff); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 598cfdb122..ca26628704 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -181,7 +181,7 @@ static u32 get_COMP2(const ramctr_timing *ctrl) static u32 get_COMP1(ramctr_timing *ctrl, const int channel) { const union comp_ofst_1_reg orig_comp = { - .raw = MCHBAR32(CRCOMPOFST1_ch(channel)), + .raw = mchbar_read32(CRCOMPOFST1_ch(channel)), }; if (IS_SANDY_CPU(ctrl->cpu) && !IS_SANDY_CPU_D2(ctrl->cpu)) { @@ -554,7 +554,7 @@ static void dram_freq(ramctr_timing *ctrl) * The MPLL will never lock if the requested frequency is already set. * Exit early to prevent a system hang. */ - reg1 = MCHBAR32(MC_BIOS_DATA); + reg1 = mchbar_read32(MC_BIOS_DATA); val2 = (u8) reg1; if (val2) return; @@ -565,18 +565,18 @@ static void dram_freq(ramctr_timing *ctrl) reg1 |= (1 << 8); /* Use 100MHz reference clock */ reg1 |= (1 << 31); /* Set running bit */ - MCHBAR32(MC_BIOS_REQ) = reg1; + mchbar_write32(MC_BIOS_REQ, reg1); int i = 0; printk(BIOS_DEBUG, "MPLL busy... "); while (reg1 & (1 << 31)) { udelay(10); i++; - reg1 = MCHBAR32(MC_BIOS_REQ); + reg1 = mchbar_read32(MC_BIOS_REQ); } printk(BIOS_DEBUG, "done in %d us\n", i * 10); /* Step 3 - Verify lock frequency */ - reg1 = MCHBAR32(MC_BIOS_DATA); + reg1 = mchbar_read32(MC_BIOS_DATA); val2 = (u8) reg1; if (val2 >= ctrl->FRQ) { printk(BIOS_DEBUG, "MPLL frequency is set at : %d MHz\n", @@ -594,12 +594,12 @@ static void dram_ioregs(ramctr_timing *ctrl) /* IO clock */ FOR_ALL_CHANNELS { - MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; + mchbar_write32(GDCRCLKRANKSUSED_ch(channel), ctrl->rankmap[channel]); } /* IO command */ FOR_ALL_CHANNELS { - MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; + mchbar_write32(GDCRCTLRANKSUSED_ch(channel), ctrl->rankmap[channel]); } /* IO control */ @@ -609,23 +609,23 @@ static void dram_ioregs(ramctr_timing *ctrl) /* Perform RCOMP */ printram("RCOMP..."); - while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) + while (!(mchbar_read32(RCOMP_TIMER) & (1 << 16))) ; printram("done\n"); /* Set COMP2 */ - MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl); + mchbar_write32(CRCOMPOFST2, get_COMP2(ctrl)); printram("COMP2 done\n"); /* Set COMP1 */ FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(CRCOMPOFST1_ch(channel)) = get_COMP1(ctrl, channel); + mchbar_write32(CRCOMPOFST1_ch(channel), get_COMP1(ctrl, channel)); } printram("COMP1 done\n"); printram("FORCE RCOMP and wait 20us..."); - MCHBAR32(M_COMP) |= (1 << 8); + mchbar_setbits32(M_COMP, 1 << 8); udelay(20); printram("done\n"); } @@ -654,7 +654,7 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ } /* Set version register */ - MCHBAR32(MRC_REVISION) = 0xc04eb002; + mchbar_write32(MRC_REVISION, 0xc04eb002); /* Enable crossover */ dram_xover(ctrl); @@ -663,16 +663,16 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ dram_timing_regs(ctrl); /* Power mode preset */ - MCHBAR32(PM_THML_STAT) = 0x5500; + mchbar_write32(PM_THML_STAT, 0x5500); /* Set scheduler chicken bits */ - MCHBAR32(SCHED_CBIT) = 0x10100005; + mchbar_write32(SCHED_CBIT, 0x10100005); /* Set up watermarks and starvation counter */ set_wmm_behavior(ctrl->cpu); /* Clear IO reset bit */ - MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); + mchbar_clrbits32(MC_INIT_STATE_G, 1 << 5); /* Set MAD-DIMM registers */ dram_dimm_set_mapping(ctrl, 1); diff --git a/src/northbridge/intel/sandybridge/raminit_shared.c b/src/northbridge/intel/sandybridge/raminit_shared.c index 426035d810..543d285e9b 100644 --- a/src/northbridge/intel/sandybridge/raminit_shared.c +++ b/src/northbridge/intel/sandybridge/raminit_shared.c @@ -21,15 +21,15 @@ void report_memory_config(void) u32 addr_decoder_common, addr_decode_ch[2]; int i; - addr_decoder_common = MCHBAR32(MAD_CHNL); - addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); - addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); + addr_decoder_common = mchbar_read32(MAD_CHNL); + addr_decode_ch[0] = mchbar_read32(MAD_DIMM_CH0); + addr_decode_ch[1] = mchbar_read32(MAD_DIMM_CH1); - const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; + const int refclk = mchbar_read32(MC_BIOS_REQ) & 0x100 ? 100 : 133; printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); + (mchbar_read32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", (addr_decoder_common >> 0) & 3, diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 49f334e397..d6e7ee9025 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -33,7 +33,7 @@ void mainboard_romstage_entry(void) { int s3resume = 0; - if (MCHBAR16(SSKPD_HI) == 0xCAFE) + if (mchbar_read16(SSKPD_HI) == 0xcafe) system_reset(); enable_lapic(); |