diff options
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.h | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h index bfdbe8d3eb..b41aa855aa 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.h +++ b/src/northbridge/intel/sandybridge/raminit_native.h @@ -24,5 +24,6 @@ void read_spd(spd_raw_data *spd, u8 addr); void mainboard_get_spd(spd_raw_data *spd); void rcba_config(void); void pch_enable_lpc(void); +void mainboard_early_init(int s3resume); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 34d759f419..3d05f8e3fa 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -103,6 +103,9 @@ void main(unsigned long bist) s3resume = southbridge_detect_s3_resume(); post_code(0x38); + + mainboard_early_init(s3resume); + /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); |