5 files changed, 0 insertions, 7 deletions
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c
index 489340a2bd..7378391507 100644
--- a/src/northbridge/intel/x4x/dq_dqs.c
+++ b/src/northbridge/intel/x4x/dq_dqs.c
@@ -129,7 +129,6 @@ static int decrement_dq_dqs(const struct sysinfo *s,
 	return CB_SUCCESS;
 }
 
-
 #define WT_PATTERN_SIZE 80
 
 static const u32 write_training_schedule[WT_PATTERN_SIZE] = {
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index db0ab9c9fb..aa737f391f 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -104,7 +104,6 @@ static uintptr_t northbridge_get_tseg_base(void)
 	return pci_read_config32(HOST_BRIDGE, D0F0_TSEG);
 }
 
-
 /* Depending of UMA and TSEG configuration, TSEG might start at any
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index a62771d676..c68c70bd31 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -99,7 +99,6 @@ static void select_cas_dramfreq_ddr2(struct sysinfo *s,
 		try_cas--;
 	}
 
-
 	if ((s->selected_timings.CAS < 3) || (s->selected_timings.tclk == 0))
 		die("Could not find common memory frequency and CAS\n");
 
@@ -411,7 +410,6 @@ static int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd,
 	return CB_SUCCESS;
 }
 
-
 static void select_discrete_timings(struct sysinfo *s,
 				const struct abs_timings *timings)
 {
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 89228f6792..2c250683a1 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -33,7 +33,6 @@ u32 ddr_to_mhz(u32 speed)
 	return mhz[speed];
 }
 
-
 static void program_crossclock(struct sysinfo *s)
 {
 	u8 i, j;
@@ -1283,7 +1282,6 @@ u32 test_address(int channel, int rank)
 	return channel * 512 * MiB + rank * 128 * MiB;
 }
 
-
 /* DDR3 Rank1 Address mirror
  * swap the following pins:
  * A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */
diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c
index 3cd4879787..e4a80d8441 100644
--- a/src/northbridge/intel/x4x/raminit_tables.c
+++ b/src/northbridge/intel/x4x/raminit_tables.c
@@ -290,7 +290,6 @@ const u8 post_jedec_tab[3][4][2]= /* [FSB][DDR freq][17:13 or 12:8] */
 	},
 };
 
-
 const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */
 		/* 115h[15:0]	117h[23:0] */
 	{ /* 1N mode */