diff options
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/Kconfig | 88 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/Makefile.inc | 34 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/acpi.c | 71 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl | 131 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl | 36 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/chip.h | 69 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/fsp/Kconfig | 45 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc | 17 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 160 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h | 48 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/memmap.c | 42 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/northbridge.c | 251 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/northbridge.h | 69 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/port_access.c | 65 |
14 files changed, 0 insertions, 1126 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig deleted file mode 100644 index bc7352641c..0000000000 --- a/src/northbridge/intel/fsp_rangeley/Kconfig +++ /dev/null @@ -1,88 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Google Inc. -## Copyright (C) 2013 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config NORTHBRIDGE_INTEL_FSP_RANGELEY - bool - select CPU_INTEL_FSP_MODEL_406DX - -if NORTHBRIDGE_INTEL_FSP_RANGELEY - -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - -choice - prompt "Set TSEG Size" - default SET_TSEG_1MB if SET_DEFAULT_TSEG_1MB - default SET_TSEG_2MB if SET_DEFAULT_TSEG_2MB - default SET_TSEG_4MB if SET_DEFAULT_TSEG_4MB - default SET_TSEG_8MB if SET_DEFAULT_TSEG_8MB - -config SET_TSEG_1MB - bool "1 MB" - help - Set the TSEG area to 1 MB. - -config SET_TSEG_2MB - bool "2 MB" - help - Set the TSEG area to 2 MB. - -config SET_TSEG_4MB - bool "4 MB" - help - Set the TSEG area to 4 MB. - -config SET_TSEG_8MB - bool "8 MB" - help - Set the TSEG area to 8 MB. -endchoice - -config SMM_TSEG_SIZE - hex - default 0x200000 if SET_TSEG_2MB - default 0x400000 if SET_TSEG_4MB - default 0x800000 if SET_TSEG_8MB - default 0x100000 # SET_TSEG_1MB - -config SMM_RESERVED_SIZE - hex - default 0x200000 if SET_TSEG_2MB - default 0x400000 if SET_TSEG_4MB - default 0x800000 if SET_TSEG_8MB - default 0x100000 # SET_TSEG_1MB - -config SET_DEFAULT_TSEG_1MB - bool - default n - -config SET_DEFAULT_TSEG_2MB - bool - default n - -config SET_DEFAULT_TSEG_4MB - bool - default n - -config SET_DEFAULT_TSEG_8MB - bool - default n - -# Rangeley Specific FSP Kconfig -source src/northbridge/intel/fsp_rangeley/fsp/Kconfig - -endif # NORTHBRIDGE_INTEL_FSP_RANGELEY diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc deleted file mode 100644 index f02e3c4aec..0000000000 --- a/src/northbridge/intel/fsp_rangeley/Makefile.inc +++ /dev/null @@ -1,34 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2010 Google Inc. -# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY),y) - -subdirs-y += fsp -ramstage-y += northbridge.c - -ramstage-y += acpi.c -ramstage-y += port_access.c - -romstage-y += memmap.c -romstage-y += ../../../arch/x86/walkcbfs.S -romstage-y += port_access.c - -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR) - -CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/ -CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_rangeley/fsp - -endif diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c deleted file mode 100644 index 0c52d52588..0000000000 --- a/src/northbridge/intel/fsp_rangeley/acpi.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 The Chromium OS Authors - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <arch/acpi.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <arch/acpigen.h> - -#include "northbridge.h" - -unsigned long acpi_fill_mcfg(unsigned long current) -{ - struct device *dev; - u32 pciexbar = 0; - u32 pciexbar_reg; - int max_buses; - int pci_dev_id; - - for (pci_dev_id = PCI_DEVICE_ID_RG_MIN; pci_dev_id <= PCI_DEVICE_ID_RG_MAX; pci_dev_id++) { - dev = dev_find_device(PCI_VENDOR_ID_INTEL, pci_dev_id, 0); - if (dev) - break; - } - - if (!dev) - return current; - - pciexbar_reg = sideband_read(B_UNIT, BECREG); - - /* MMCFG not supported or not enabled. */ - if (!(pciexbar_reg & (1 << 0))) - return current; - - /* 256MB ECAM range */ - pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - max_buses = 256; - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); - - return current; -} - -void northbridge_acpi_fill_ssdt_generator(struct device *device) -{ - u32 bmbound; - char pscope[] = "\\_SB.PCI0"; - - bmbound = sideband_read(B_UNIT, BMBOUND); - acpigen_write_scope(pscope); - acpigen_write_name_dword("BMBD", bmbound); - acpigen_pop_len(); - generate_cpu_entries(device); -} diff --git a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl deleted file mode 100644 index 4e9bc324c6..0000000000 --- a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl +++ /dev/null @@ -1,131 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI - -Name(_BBN, 0) - -// This is in the SSDT and can be accessed by the DSDT -External (BMBD) - -// Current Resource Settings -Name (MCRS, ResourceTemplate() -{ - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR3) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0, 0x00000000, - 0,,, PM01) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) -}) // End MCRS - -Method (_CRS, 0, Serialized) -{ - // Find PCI resource area in MCRS - CreateDwordField(MCRS, ^PM01._MIN, PMIN) - CreateDwordField(MCRS, ^PM01._MAX, PMAX) - CreateDwordField(MCRS, ^PM01._LEN, PLEN) - - // Fix up PCI memory region - // Start with Top of Lower Usable DRAM - // Memory goes from BMBOUND to CONFIG_MMCONF_BASE_ADDRESS (PM01 above) - Store (BMBD, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) - Add(Subtract(PMAX, PMIN), 1, PLEN) // Store Memory Size - - Return (MCRS) -} // End _CRS diff --git a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl b/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl deleted file mode 100644 index ba74fcb696..0000000000 --- a/src/northbridge/intel/fsp_rangeley/acpi/rangeley.asl +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../northbridge.h" -#include "hostbridge.asl" - -/* PCI Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID("PNP0C02")) - Name (_UID, 1) - - Name (PDRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, DEFAULT_ECBASE, 0x10000000) - }) - - // Current Resource Settings - Method (_CRS, 0, Serialized) - { - Return(PDRS) - } -} diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h deleted file mode 100644 index 9c7d5a2b14..0000000000 --- a/src/northbridge/intel/fsp_rangeley/chip.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _FSP_RANGELEY_CHIP_H_ -#define _FSP_RANGELEY_CHIP_H_ - -#include <arch/acpi.h> -#include <drivers/intel/fsp1_0/fsp_values.h> - -struct northbridge_intel_fsp_rangeley_config { - - /* Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1) */ - /* Valid values: 0 - 15 */ - uint8_t MrcRmtCpgcExpLoopCntValue; - /* Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1) */ - /* Valid values: 0 - 15 */ - uint8_t MrcRmtCpgcNumBursts; - /* DIMM SPD SMBus Addresses */ - uint8_t SpdBaseAddress_0_0; - uint8_t SpdBaseAddress_0_1; - uint8_t SpdBaseAddress_1_0; - uint8_t SpdBaseAddress_1_1; - - uint8_t EnableLan; - uint8_t EnableSata2; - uint8_t EnableSata3; - uint8_t EnableIQAT; - uint8_t EnableUsb20; - uint8_t PrintDebugMessages; - uint8_t Fastboot; - uint8_t EccSupport; - uint8_t SpdWriteProtect; - /* Enable = Memory Down, Disable = DIMM */ - uint8_t MemoryDown; - /* Enable the Rank Margin Tool, needs PrintDebugMessages */ - uint8_t MrcRmtSupport; - - /* PCIe port bifurcation control */ - uint8_t Bifurcation; - #define BIFURCATION_4_4_4_4 0 - #define BIFURCATION_4_4_8 1 - #define BIFURCATION_8_4_4 2 - #define BIFURCATION_8_8 3 - #define BIFURCATION_16 4 - - /* PCIe port de-emphasis control */ - uint8_t PcdPcieRootPort1DeEmphasis; - uint8_t PcdPcieRootPort2DeEmphasis; - uint8_t PcdPcieRootPort3DeEmphasis; - uint8_t PcdPcieRootPort4DeEmphasis; - #define DE_EMPHASIS_DEFAULT 0 - #define DE_EMPHASIS_MINUS_6_0_DB 1 - #define DE_EMPHASIS_MINUS_3_5_DB 2 -}; - -#endif diff --git a/src/northbridge/intel/fsp_rangeley/fsp/Kconfig b/src/northbridge/intel/fsp_rangeley/fsp/Kconfig deleted file mode 100644 index 67ed66b9ed..0000000000 --- a/src/northbridge/intel/fsp_rangeley/fsp/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config RANGELEY_FSP_SPECIFIC_OPTIONS - def_bool y - select PLATFORM_USES_FSP1_0 - select USE_GENERIC_FSP_CAR_INC - select FSP_USES_UPD - select ENABLE_MRC_CACHE #rangeley FSP always needs MRC data - -config FSP_FILE - string - default "../intel/fsp/rangeley/FvFsp.bin" - help - The path and filename of the Intel FSP binary for this platform. - -config FSP_LOC - hex - default 0xfff80000 - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with Intel's BCT (tool). - - The Rangeley FSP is built with a preferred base address of 0xFFF80000 - -config DCACHE_RAM_BASE - hex - default 0xfef00000 - -config DCACHE_RAM_SIZE - hex - default 0x4000 diff --git a/src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc b/src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc deleted file mode 100644 index 09c5bc506d..0000000000 --- a/src/northbridge/intel/fsp_rangeley/fsp/Makefile.inc +++ /dev/null @@ -1,17 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2014 Sage Electronic Engineering, LLC. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -ramstage-y += chipset_fsp_util.c -romstage-y += chipset_fsp_util.c diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c deleted file mode 100644 index 9acce5b8b9..0000000000 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <console/console.h> -#include <bootstate.h> -#include <cbmem.h> -#include <device/device.h> -#include <southbridge/intel/fsp_rangeley/pci_devs.h> -#include <drivers/intel/fsp1_0/fsp_util.h> -#include <fspvpd.h> -#include <fspbootmode.h> -#include "../chip.h" - -/* Copy the default UPD region and settings to a buffer for modification */ -static void GetUpdDefaultFromFsp - (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData) -{ - VPD_DATA_REGION *VpdDataRgnPtr; - UPD_DATA_REGION *UpdDataRgnPtr; - VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset - + FspInfo->ImageBase); - UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32) - (VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase); - memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION)); -} - -typedef struct northbridge_intel_fsp_rangeley_config config_t; - -/** - * Update the UPD data based on values from devicetree.cb - * - * @param UpdData Pointer to the UPD Data structure - */ -static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) -{ - DEVTREE_CONST struct device *dev; - DEVTREE_CONST config_t *config; - printk(BIOS_DEBUG, "Configure Default UPD Data\n"); - - dev = pcidev_path_on_root(SOC_DEVFN_SOC); - config = dev->chip_info; - - /* Set SPD addresses */ - if (config->SpdBaseAddress_0_0) { - UpdData->PcdSpdBaseAddress_0_0 = config->SpdBaseAddress_0_0; - } - if (config->SpdBaseAddress_0_1) { - UpdData->PcdSpdBaseAddress_0_1 = config->SpdBaseAddress_0_1; - } - if (config->SpdBaseAddress_1_0) { - UpdData->PcdSpdBaseAddress_1_0 = config->SpdBaseAddress_1_0; - } - if (config->SpdBaseAddress_1_1) { - UpdData->PcdSpdBaseAddress_1_1 = config->SpdBaseAddress_1_1; - } - if (config->EccSupport) { - UpdData->PcdEccSupport = config->EccSupport; - } - if (config->PrintDebugMessages) { - UpdData->PcdPrintDebugMessages = config->PrintDebugMessages; - } - if (config->Bifurcation) { - UpdData->PcdBifurcation = config->Bifurcation; - } - if (config->MemoryDown) { - UpdData->PcdMemoryDown = config->MemoryDown; - } - - UpdData->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE >> 20; - - if (config->MrcRmtCpgcExpLoopCntValue) { - UpdData->PcdMrcRmtCpgcExpLoopCntValue = - config->MrcRmtCpgcExpLoopCntValue; - } - if (config->MrcRmtCpgcNumBursts) { - UpdData->PcdMrcRmtCpgcNumBursts = config->MrcRmtCpgcNumBursts; - } - if (CONFIG(ENABLE_FSP_FAST_BOOT)) - UpdData->PcdFastboot = UPD_ENABLE; - - /* - * Loop through all the SOC devices in the devicetree - * enabling and disabling them as requested. - */ - for (; dev; dev = dev->sibling) { - - if (dev->path.type != DEVICE_PATH_PCI) - continue; - - switch (dev->path.pci.devfn) { - case SOC_DEVFN_GBE1: - case SOC_DEVFN_GBE2: - case SOC_DEVFN_GBE3: - case SOC_DEVFN_GBE4: - UpdData->PcdEnableLan |= dev->enabled; - printk(BIOS_DEBUG, "PcdEnableLan %d\n", - UpdData->PcdEnableLan); - break; - case SOC_DEVFN_SATA2: - UpdData->PcdEnableSata2 = dev->enabled; - printk(BIOS_DEBUG, "PcdEnableSata2 %d\n", - UpdData->PcdEnableSata2); - break; - case SOC_DEVFN_SATA3: - UpdData->PcdEnableSata3 = dev->enabled; - printk(BIOS_DEBUG, "PcdEnableSata3 %d\n", - UpdData->PcdEnableSata3); - break; - case SOC_DEVFN_IQAT: - UpdData->PcdEnableIQAT |= dev->enabled; - printk(BIOS_DEBUG, "PcdEnableIQAT %d\n", - UpdData->PcdEnableIQAT); - break; - case SOC_DEVFN_USB2: - UpdData->PcdEnableUsb20 = dev->enabled; - printk(BIOS_DEBUG, "PcdEnableUsb20 %d\n", - UpdData->PcdEnableUsb20); - break; - } - } - - /* Set PCIe de-emphasis */ - UPD_DEFAULT_CHECK(PcdPcieRootPort1DeEmphasis); - UPD_DEFAULT_CHECK(PcdPcieRootPort2DeEmphasis); - UPD_DEFAULT_CHECK(PcdPcieRootPort3DeEmphasis); - UPD_DEFAULT_CHECK(PcdPcieRootPort4DeEmphasis); -} - -/* Set up the Rangeley specific structures for the call into the FSP */ -void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, - FSP_INFO_HEADER *fsp_ptr) -{ - FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; - - /* Initialize the UPD Data */ - GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); - ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); - pFspInitParams->NvsBufferPtr = NULL; - pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; - - /* Find the fastboot cache that was saved in the ROM */ - pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); - - return; -} diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h deleted file mode 100644 index b9d64c15f6..0000000000 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef CHIPSET_FSP_UTIL_H -#define CHIPSET_FSP_UTIL_H - -#include <fsptypes.h> -#include <fspfv.h> -#include <fspffs.h> -#include <fspapi.h> -#include <fspplatform.h> -#include <fspinfoheader.h> -#include <fsphob.h> -#include <fspvpd.h> - -#define FSP_RESERVE_MEMORY_SIZE 0x200000 - -#define FSP_INFO_HEADER_GUID \ - { \ - 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ - } - -#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ - { \ - 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0} \ - } - -/* - *The FSP Image ID is different for each platform's FSP and - * can be used to verify that the right FSP binary is loaded. - * For the Rangeley FSP, the Image Id is "AVN-FSP0". - */ -#define FSP_IMAGE_ID_DWORD0 0x2d4e5641 /* 'AVN-' */ -#define FSP_IMAGE_ID_DWORD1 0x30505346 /* 'FSP0' */ - -#endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/northbridge/intel/fsp_rangeley/memmap.c b/src/northbridge/intel/fsp_rangeley/memmap.c deleted file mode 100644 index 275ddd3ac1..0000000000 --- a/src/northbridge/intel/fsp_rangeley/memmap.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <device/pci_def.h> -#include <drivers/intel/fsp1_0/fsp_util.h> - -#include "northbridge.h" - -static uintptr_t smm_region_start(void) -{ - /* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. - */ - uintptr_t tom = sideband_read(B_UNIT, BMBOUND); - uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; - if (bsmmrrl) { - tom = bsmmrrl; - } - - return tom; -} - -void *cbmem_top_chipset(void) -{ - return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE); -} diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c deleted file mode 100644 index 4ebbe7ec15..0000000000 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ /dev/null @@ -1,251 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/acpi.h> -#include <device/pci_ops.h> -#include <stdint.h> -#include <cpu/intel/fsp_model_406dx/model_406dx.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <stdlib.h> -#include <cpu/cpu.h> -#include <drivers/intel/fsp1_0/fsp_util.h> -#include <cpu/x86/lapic.h> - -#include "chip.h" -#include "northbridge.h" - -static int bridge_revision_id = -1; - -int bridge_silicon_revision(void) -{ - if (bridge_revision_id < 0) { - uint8_t stepping = cpuid_eax(1) & 0xf; - uint8_t bridge_id = pci_read_config16( - pcidev_on_root(0, 0), - PCI_DEVICE_ID) & 0xf0; - bridge_revision_id = bridge_id | stepping; - } - return bridge_revision_id; -} - -/* Reserve everything between A segment and 1MB: - * - * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) - * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI - */ -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 384; - -static int get_pcie_bar(u32 *base) -{ - struct device *dev; - u32 pciexbar_reg; - - *base = 0; - - dev = pcidev_on_root(0, 0); - if (!dev) - return 0; - - pciexbar_reg = sideband_read(B_UNIT, BECREG); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | - (1 << 28)); - return 256; - -} - -static void add_fixed_resources(struct device *dev, int index) -{ - struct resource *resource; - - resource = new_resource(dev, index++); /* Local APIC */ - resource->base = LAPIC_DEFAULT_BASE; - resource->size = 0x00001000; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); -} - -static void mc_add_dram_resources(struct device *dev) -{ - u32 tomlow, bmbound, bsmmrrl, bsmmrrh; - u64 bmbound_hi; - int index = 0; - - /* - * These are the host memory ranges : - * - 0 -> SMM (SMMRRL) : cacheable - * - SMM -> LOW TOM (BMBOUND) : cacheable WP - * - 4GB -> HIGH TOM (BMBOUND_HI): cacheable - * - */ - - tomlow = bmbound = sideband_read(B_UNIT, BMBOUND); - printk(BIOS_SPEW, "Top of Low Used DRAM (BMBOUND): 0x%08x\n", bmbound); - - bmbound_hi = (u64)(sideband_read(B_UNIT, BMBOUND_HI)) << 4; - printk(BIOS_SPEW, "Top of Upper Used DRAM (BMBOUND_HI): 0x%llx\n", bmbound_hi); - - bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; - bsmmrrh = ((sideband_read(B_UNIT, BSMMRRH) + 1) << 20) - 1; - if (bsmmrrl) { - tomlow = bsmmrrl; - printk(BIOS_DEBUG, "SMM memory location: 0x%x SMM memory size: 0x%x\n", bsmmrrl, (bsmmrrh - bsmmrrl + 1)); - printk(BIOS_DEBUG, "Subtracting %dM for SMM\n", (bmbound - bsmmrrl) >> 20); - } - tomlow -= FSP_RESERVE_MEMORY_SIZE; - printk(BIOS_SPEW, "Available memory below 4GB: 0x%08x (%dM)\n", tomlow, tomlow >> 20); - - /* Report the memory regions. */ - ram_resource(dev, index++, 0, legacy_hole_base_k); - ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, - ((tomlow >> 10) - (legacy_hole_base_k + legacy_hole_size_k))); - - mmio_resource(dev, index++, tomlow >> 10, (bmbound - bsmmrrl) >> 10); - - if (bmbound_hi > 0x100000000) { - ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); - printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (bmbound_hi - 0x100000000) >> 20); - } - - add_fixed_resources(dev, index); -} - -static void mc_read_resources(struct device *dev) -{ - u32 pcie_config_base; - int buses; - - /* Call the normal read_resources */ - pci_dev_read_resources(dev); - - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - buses = get_pcie_bar(&pcie_config_base); - if (buses) { - struct resource *resource = new_resource(dev, 0xcf); - mmconf_resource_init(resource, pcie_config_base, buses); - } - - /* Calculate and add DRAM resources. */ - mc_add_dram_resources(dev); -} - -static void pci_domain_set_resources(struct device *dev) -{ - /* - * Assign memory resources for PCI devices - */ - mc_add_dram_resources(dev); - - assign_resources(dev->link_list); -} - -static void mc_set_resources(struct device *dev) -{ - /* Call the normal set_resources */ - pci_dev_set_resources(dev); -} - -static void northbridge_init(struct device *dev) -{ -} - -static void northbridge_enable(struct device *dev) -{ -} - -static struct pci_operations intel_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, -}; - -static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = mc_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .acpi_fill_ssdt_generator = northbridge_acpi_fill_ssdt_generator, - .enable = northbridge_enable, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, -}; - -/* - * The following entries are taken from Intel document number 510524, rev 1.6: - * Rangeley SoC External Design Specification (EDS) - * Section 10.3 PCI Configuration Space - * Table 10-6. PCI Devices and Functions - * - * These are the Device ID values for the item at bus 0, device 0, function 0. - */ -static const unsigned short pci_device_ids[] = { - 0x1f00, 0x1f01, 0x1f02, 0x1f03, - 0x1f04, 0x1f05, 0x1f06, 0x1f07, - 0x1f08, 0x1f09, 0x1f0a, 0x1f0b, - 0x1f0c, 0x1f0d, 0x1f0e, 0x1f0f, - 0, /* -- END OF LIST -- */ -}; - -static const struct pci_driver mc_driver __pci_driver = { - .ops = &mc_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; - -static void cpu_bus_init(struct device *dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = cpu_bus_init, - .scan_bus = 0, -}; - -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_intel_fsp_rangeley_ops = { - CHIP_NAME("Intel Rangeley Northbridge") - .enable_dev = enable_dev, -}; diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h deleted file mode 100644 index fd5fa05a39..0000000000 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ - -#define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS - -/* Everything below this line is ignored in the DSDT */ -#ifndef __ACPI__ - -#include <device/device.h> - -/* Device 0:0.0 PCI configuration space (Host Bridge) */ - -/* SideBand B-UNIT */ -#define B_UNIT 3 - #define BNOCACHE 0x23 - #define BNOCACHECTL 0x24 - #define BMBOUND 0x25 - #define BMBOUND_HI 0x26 - #define BECREG 0x27 - #define BMISC 0x28 - #define BSMMRRL 0x2E - #define BSMMRRH 0x2F - #define BIMR0L 0x80 - #define BIMR0H 0x81 - #define BIMR0RAC 0x82 - #define BIMR0WAC 0x83 - -/* SideBand C-UNIT */ -#define C_UNIT 8 - -/* SideBand D-UNIT */ -#define D_UNIT 1 - -/* SideBand P-UNIT */ -#define P_UNIT 4 - -#ifndef __ASSEMBLER__ - -#define PCI_DEVICE_ID_RG_MIN 0x1F00 -#define PCI_DEVICE_ID_RG_MAX 0x1F0F -#define SKPAD 0xFC - -int bridge_silicon_revision(void); -void rangeley_late_initialization(void); -u32 sideband_read(int port, int reg); -void sideband_write(int port, int reg, long data); - -void northbridge_acpi_fill_ssdt_generator(struct device *device); - -#endif /* #ifndef __ASSEMBLER__ */ -#endif /* #ifndef __ACPI__ */ -#endif /* __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ */ diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c deleted file mode 100644 index 75d1bb2b05..0000000000 --- a/src/northbridge/intel/fsp_rangeley/port_access.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009-2010 iWave Systems - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <cpu/x86/lapic.h> -#include "northbridge.h" - -/* - * Restricted Access Regions: - * - * MCR - Message Control Register - * 31 24 16 8 4 0 - * ---------------------------------------------------------------------------- - * | | | Target | Write | | - * | Opcode | Port | register | byte | Reserved | - * | | | Address | Enables | | - * ---------------------------------------------------------------------------- - * - * MDR - Message Data Register - * 31 0 - * ---------------------------------------------------------------------------- - * | | - * | Data | - * | | - * ---------------------------------------------------------------------------- - */ - -#define MSG_OPCODE_READ (0x10 << 24) -#define MSG_OPCODE_WRITE (0x11 << 24) - -#define MCR 0xD0 -#define MDR 0xD4 -#define MCRE 0xD8 - -u32 sideband_read(int port, int reg) -{ - pci_write_config32(PCI_DEV(0, 0, 0), MCR, - (MSG_OPCODE_READ | (port << 16) | (reg << 8))); - return pci_read_config32(PCI_DEV(0, 0, 0), MDR); -} - -void sideband_write(int port, int reg, long data) -{ - pci_write_config32(PCI_DEV(0, 0, 0), MDR, data); - pci_write_config32(PCI_DEV(0, 0, 0), MCR, - (MSG_OPCODE_WRITE | (port << 16) | (reg << 8) | (0xF << 4))); - pci_read_config32(PCI_DEV(0, 0, 0), MDR); -} |