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Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/sandybridge/early_init.c14
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c14
2 files changed, 4 insertions, 24 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index ad579c6fc3..b923065091 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -27,20 +27,6 @@
static void sandybridge_setup_bars(void)
{
- /* Setting up Southbridge. In the northbridge code. */
- printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-
- pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
-
- printk(BIOS_DEBUG, " done.\n");
-
- printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
- RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
- outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
- printk(BIOS_DEBUG, " done.\n");
-
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 6f2a8f1472..3fab3be85d 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -28,10 +28,9 @@
#include <device/device.h>
#include <northbridge/intel/sandybridge/chip.h>
#include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmclib.h>
-static void early_pch_init(void)
+static void early_pch_reset_pmcon(void)
{
u8 reg8;
@@ -56,13 +55,8 @@ void mainboard_romstage_entry(unsigned long bist)
if (bist == 0)
enable_lapic();
- pch_enable_lpc();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&mainboard_gpio_map);
+ /* Init LPC, GPIO, BARs, disable watchdog ... */
+ early_pch_init();
/* Initialize superio */
mainboard_config_superio();
@@ -101,7 +95,7 @@ void mainboard_romstage_entry(unsigned long bist)
post_code(0x3b);
/* Perform some initialization that must run before stage2 */
- early_pch_init();
+ early_pch_reset_pmcon();
post_code(0x3c);
southbridge_configure_default_intmap();