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-rw-r--r--src/northbridge/intel/e7520/Kconfig6
-rw-r--r--src/northbridge/intel/e7520/raminit.c6
-rw-r--r--src/northbridge/intel/e7525/Kconfig6
-rw-r--r--src/northbridge/intel/e7525/raminit.c6
-rw-r--r--src/northbridge/intel/i3100/Kconfig6
-rw-r--r--src/northbridge/intel/i3100/raminit.c6
6 files changed, 21 insertions, 15 deletions
diff --git a/src/northbridge/intel/e7520/Kconfig b/src/northbridge/intel/e7520/Kconfig
index 426db8b12f..ef2b7f65fe 100644
--- a/src/northbridge/intel/e7520/Kconfig
+++ b/src/northbridge/intel/e7520/Kconfig
@@ -1,3 +1,9 @@
config NORTHBRIDGE_INTEL_E7520
bool
+if NORTHBRIDGE_INTEL_E7520
+config DIMM_MAP_LOGICAL
+ hex
+ default 0x1248
+
+endif
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 235ce44f2b..6eed1964e9 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -1078,12 +1078,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Starting SDRAM Enable\n");
/* 0x80 */
-#ifdef DIMM_MAP_LOGICAL
pci_write_config32(PCI_DEV(0, 0x00, 0), DRM,
- 0x00210000 | DIMM_MAP_LOGICAL);
-#else
- pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00211248);
-#endif
+ 0x00210000 | CONFIG_DIMM_MAP_LOGICAL);
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
diff --git a/src/northbridge/intel/e7525/Kconfig b/src/northbridge/intel/e7525/Kconfig
index d8bff2225b..04e3d8b619 100644
--- a/src/northbridge/intel/e7525/Kconfig
+++ b/src/northbridge/intel/e7525/Kconfig
@@ -1,3 +1,9 @@
config NORTHBRIDGE_INTEL_E7525
bool
+if NORTHBRIDGE_INTEL_E7525
+config DIMM_MAP_LOGICAL
+ hex
+ default 0x1248
+
+endif
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index b482bb9fec..aabe8cfba5 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -1055,12 +1055,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Starting SDRAM Enable\n");
/* 0x80 */
-#ifdef DIMM_MAP_LOGICAL
pci_write_config32(ctrl->f0, DRM,
- 0x00210000 | DIMM_MAP_LOGICAL);
-#else
- pci_write_config32(ctrl->f0, DRM, 0x00211248);
-#endif
+ 0x00210000 | CONFIG_DIMM_MAP_LOGICAL);
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig
index a85162310e..079004bda9 100644
--- a/src/northbridge/intel/i3100/Kconfig
+++ b/src/northbridge/intel/i3100/Kconfig
@@ -1,3 +1,9 @@
config NORTHBRIDGE_INTEL_I3100
bool
+if NORTHBRIDGE_INTEL_I3100
+config DIMM_MAP_LOGICAL
+ hex
+ default 0x1248
+
+endif
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 5afddb7d9e..86e610feb3 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -973,12 +973,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug("Starting SDRAM Enable\n");
/* 0x80 */
-#ifdef DIMM_MAP_LOGICAL
pci_write_config32(ctrl->f0, DRM,
- 0x00410000 | DIMM_MAP_LOGICAL);
-#else
- pci_write_config32(ctrl->f0, DRM, 0x00411248);
-#endif
+ 0x00410000 | CONFIG_DIMM_MAP_LOGICAL);
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {