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-rw-r--r--src/northbridge/intel/gm45/ram_calc.c7
-rw-r--r--src/northbridge/intel/i945/ram_calc.c7
-rw-r--r--src/northbridge/intel/pineview/ram_calc.c7
-rw-r--r--src/northbridge/intel/x4x/ram_calc.c7
4 files changed, 12 insertions, 16 deletions
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 719c59fbd4..6795f7a61f 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -126,13 +126,12 @@ void *cbmem_top(void)
void stage_cache_external_region(void **base, size_t *size)
{
- /*
- * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+ /* The stage cache lives at the end of the TSEG region.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)(northbridge_get_tseg_base()
- + CONFIG_SMM_RESERVED_SIZE);
+ *base = (void *)((uintptr_t)northbridge_get_tseg_base()
+ + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
/* platform_enter_postcar() determines the stack to use after
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index dbe74c40cf..ac1499e0fc 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -92,13 +92,12 @@ u32 decode_igd_memory_size(const u32 gms)
void stage_cache_external_region(void **base, size_t *size)
{
- /*
- * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+ /* The stage cache lives at the end of the TSEG region.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)(northbridge_get_tseg_base()
- + CONFIG_SMM_RESERVED_SIZE);
+ *base = (void *)((uintptr_t)northbridge_get_tseg_base()
+ + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
/* platform_enter_postcar() determines the stack to use after
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index a3caaf713a..2f3ff6e921 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -142,13 +142,12 @@ void *cbmem_top(void)
void stage_cache_external_region(void **base, size_t *size)
{
- /*
- * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+ /* The stage cache lives at the end of the TSEG region.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)(northbridge_get_tseg_base()
- + CONFIG_SMM_RESERVED_SIZE);
+ *base = (void *)((uintptr_t)northbridge_get_tseg_base()
+ + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
/* platform_enter_postcar() determines the stack to use after
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 54295a9cee..dda838760d 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -137,13 +137,12 @@ void *cbmem_top(void)
void stage_cache_external_region(void **base, size_t *size)
{
- /*
- * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+ /* The stage cache lives at the end of the TSEG region.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
- *base = (void *)(northbridge_get_tseg_base()
- + CONFIG_SMM_RESERVED_SIZE);
+ *base = (void *)((uintptr_t)northbridge_get_tseg_base()
+ + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
}
/* platform_enter_postcar() determines the stack to use after