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Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/udelay.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c index 01989abb37..08301a37f6 100644 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ b/src/northbridge/intel/fsp_rangeley/udelay.c @@ -18,6 +18,8 @@ #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +#define MSR_PLATFORM_INFO 0xce + /** * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz */ |