3 files changed, 29 insertions, 22 deletions

diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index 7ed6afde3e..73f430ff48 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -131,9 +131,6 @@
 #define EPVC1RCTL	0x020	/* 32bit */
 #define EPVC1RSTS	0x026	/* 16bit */
 
-#define EPVC1MTS	0x028	/* 32bit */
-#define EPVC1IST	0x038	/* 64bit */
-
 #define EPESD		0x044	/* 32bit */
 
 #define EPLE1D		0x050	/* 32bit */
@@ -141,8 +138,6 @@
 #define EPLE2D		0x060	/* 32bit */
 #define EPLE2A		0x068	/* 64bit */
 
-#define PORTARB		0x100	/* 256bit */
-
 /*
  * DMIBAR
  */
@@ -160,10 +155,22 @@
 #define DMIVC0RCAP	0x010	/* 32bit */
 #define DMIVC0RCTL	0x014	/* 32bit */
 #define DMIVC0RSTS	0x01a	/* 16bit */
+#define  VC0NP		(1 << 1)
 
 #define DMIVC1RCAP	0x01c	/* 32bit */
 #define DMIVC1RCTL	0x020	/* 32bit */
 #define DMIVC1RSTS	0x026	/* 16bit */
+#define  VC1NP		(1 << 1)
+
+#define DMIVCPRCAP	0x028	/* 32bit */
+#define DMIVCPRCTL	0x02c	/* 32bit */
+#define DMIVCPRSTS	0x032	/* 16bit */
+#define  VCPNP		(1 << 1)
+
+#define DMIVCMRCAP	0x034	/* 32bit */
+#define DMIVCMRCTL	0x038	/* 32bit */
+#define DMIVCMRSTS	0x03e	/* 16bit */
+#define  VCMNP		(1 << 1)
 
 #define DMILE1D		0x050	/* 32bit */
 #define DMILE1A		0x058	/* 64bit */
@@ -174,12 +181,12 @@
 #define DMILCTL		0x088	/* 16bit */
 #define DMILSTS		0x08a	/* 16bit */
 
-#define DMICTL1		0x0f0	/* 32bit */
-#define DMICTL2		0x0fc	/* 32bit */
+#define DMIUESTS	0x1c4	/* 32bit */
+#define DMICESTS	0x1d0	/* 32bit */
 
 #define DMICC		0x208	/* 32bit */
 
-#define DMIDRCCFG	0xeb4	/* 32bit */
+#define DMILLTC		0x238	/* 32bit */
 
 #ifndef __ASSEMBLER__
 
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index cf014fe117..2cffa29abf 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -155,20 +155,20 @@ static void northbridge_init(struct device *dev)
 	u32 reg32;
 
 	/* Clear error status bits */
-	DMIBAR32(0x1c4) = 0xffffffff;
-	DMIBAR32(0x1d0) = 0xffffffff;
+	DMIBAR32(DMIUESTS) = 0xffffffff;
+	DMIBAR32(DMICESTS) = 0xffffffff;
 
-	reg32 = DMIBAR32(0x238);
+	reg32 = DMIBAR32(DMILLTC);
 	reg32 |= (1 << 29);
-	DMIBAR32(0x238) = reg32;
+	DMIBAR32(DMILLTC) = reg32;
 
 	reg32 = DMIBAR32(0x1f8);
 	reg32 |= (1 << 16);
 	DMIBAR32(0x1f8) = reg32;
 
-	reg32 = DMIBAR32(0x88);
+	reg32 = DMIBAR32(DMILCTL);
 	reg32 |= (1 << 1) | (1 << 0);
-	DMIBAR32(0x88) = reg32;
+	DMIBAR32(DMILCTL) = reg32;
 }
 
 /* Disable unused PEG devices based on devicetree before PCI enumeration */
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index dfe985394c..05323f1ca4 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1810,20 +1810,20 @@ static void setup_heci_uma(struct raminfo *info)
 
 	pci_read_config32(NORTHBRIDGE, DMIBAR);
 	if (info->memory_reserved_for_heci_mb) {
-		DMIBAR32(0x14) &= ~0x80;
+		DMIBAR32(DMIVC0RCTL) &= ~0x80;
 		write32(DEFAULT_RCBA   + 0x14, read32(DEFAULT_RCBA   + 0x14) & ~0x80);
-		DMIBAR32(0x20) &= ~0x80;
+		DMIBAR32(DMIVC1RCTL) &= ~0x80;
 		write32(DEFAULT_RCBA   + 0x20, read32(DEFAULT_RCBA   + 0x20) & ~0x80);
-		DMIBAR32(0x2c) &= ~0x80;
+		DMIBAR32(DMIVCPRCTL) &= ~0x80;
 		write32(DEFAULT_RCBA   + 0x30, read32(DEFAULT_RCBA   + 0x30) & ~0x80);
-		DMIBAR32(0x38) &= ~0x80;
+		DMIBAR32(DMIVCMRCTL) &= ~0x80;
 		write32(DEFAULT_RCBA   + 0x40, read32(DEFAULT_RCBA   + 0x40) & ~0x80);
 
 		write32(DEFAULT_RCBA   + 0x40, 0x87000080);	// OK
-		DMIBAR32(0x38) = 0x87000080;	// OK
+		DMIBAR32(DMIVCMRCTL) = 0x87000080;	// OK
 
 		while ((read16(DEFAULT_RCBA + 0x46) & 2) &&
-			DMIBAR16(0x3e) & 2)
+			DMIBAR16(DMIVCMRSTS) & VCMNP)
 			;
 	}
 
@@ -4600,9 +4600,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 	}
 	u32 reg1c;
 	pci_read_config32(NORTHBRIDGE, 0x40);	// = DEFAULT_EPBAR | 0x001 // OK
-	reg1c = EPBAR32(0x01c);	// = 0x8001 // OK
+	reg1c = EPBAR32(EPVC1RCAP);	// = 0x8001 // OK
 	pci_read_config32(NORTHBRIDGE, 0x40);	// = DEFAULT_EPBAR | 0x001 // OK
-	EPBAR32(0x01c) = reg1c;	// OK
+	EPBAR32(EPVC1RCAP) = reg1c;	// OK
 	MCHBAR8(0xe08);	// = 0x0
 	pci_read_config32(NORTHBRIDGE, 0xe4);	// = 0x316126
 	MCHBAR8_OR(0x1210, 2);