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-rw-r--r--src/northbridge/intel/i945/errata.c2
-rw-r--r--src/northbridge/intel/i945/raminit.h2
-rw-r--r--src/northbridge/intel/i945/romstage.c3
3 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/intel/i945/errata.c b/src/northbridge/intel/i945/errata.c
index 2b9b941aba..4d8b999d46 100644
--- a/src/northbridge/intel/i945/errata.c
+++ b/src/northbridge/intel/i945/errata.c
@@ -17,7 +17,7 @@
#include "i945.h"
#include "raminit.h"
-int fixup_i945_errata(void)
+int fixup_i945gm_errata(void)
{
u32 reg32;
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index d417169c62..26a1f5024b 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -67,5 +67,5 @@ struct sys_info {
void receive_enable_adjust(struct sys_info *sysinfo);
void sdram_initialize(int boot_path, const u8 *sdram_addresses);
-int fixup_i945_errata(void);
+int fixup_i945gm_errata(void);
#endif /* RAMINIT_H */
diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c
index 6274e099c8..2333b7d79a 100644
--- a/src/northbridge/intel/i945/romstage.c
+++ b/src/northbridge/intel/i945/romstage.c
@@ -76,7 +76,8 @@ void mainboard_romstage_entry(void)
mainboard_late_rcba_config();
/* Chipset Errata! */
- fixup_i945_errata();
+ if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
+ fixup_i945gm_errata();
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);