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-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c2
-rw-r--r--src/northbridge/intel/sandybridge/sandybridge.h1
2 files changed, 1 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 5e5cc63c38..697862f661 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -253,7 +253,7 @@ static void southbridge_fill_pei_data(struct pei_data *pei_data)
pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE;
pei_data->wdbbar = 0x04000000;
pei_data->wdbsize = 0x1000;
- pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE;
+ pei_data->rcba = (uintptr_t)DEFAULT_RCBA;
pei_data->pmbase = DEFAULT_PMBASE;
pei_data->gpiobase = DEFAULT_GPIOBASE;
pei_data->gbe_enable = dev && dev->enabled;
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 72724a3860..94a8e6f4aa 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -29,7 +29,6 @@
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
#define GFXVT_BASE 0xfed90000ULL
#define VTVC0_BASE 0xfed91000ULL