9 files changed, 17 insertions, 17 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h
index abce07aefa..dab5a9ca6f 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.h
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.h
@@ -20,7 +20,7 @@
  */
 
 #ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__
-#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ 1
+#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__
 
 #define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS
 
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h
index 9a0cf42153..d67d696d92 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.h
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h
@@ -20,7 +20,7 @@
  */
 
 #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
-#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1
+#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
 
 /* Chipset types */
 #define SANDYBRIDGE_MOBILE	0
@@ -233,4 +233,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
 
 #endif
 #endif
-#endif
+#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */
diff --git a/src/northbridge/intel/gm45/delay.h b/src/northbridge/intel/gm45/delay.h
index dda6cf4ef2..a28a3f125a 100644
--- a/src/northbridge/intel/gm45/delay.h
+++ b/src/northbridge/intel/gm45/delay.h
@@ -18,11 +18,11 @@
  */
 
 #ifndef __NORTHBRIDGE_INTEL_GM45_DELAY_H__
-#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__ 1
+#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__
 
 #include <delay.h>
 
 void ns100delay(u32);
 void udelay_from_reset(u32);
 
-#endif
+#endif /* __NORTHBRIDGE_INTEL_GM45_DELAY_H__ */
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 673160beb3..5bdf9e464d 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -19,7 +19,7 @@
  */
 
 #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__
-#define __NORTHBRIDGE_INTEL_GM45_GM45_H__ 1
+#define __NORTHBRIDGE_INTEL_GM45_GM45_H__
 
 #include "southbridge/intel/i82801ix/i82801ix.h"
 
@@ -434,4 +434,4 @@ struct acpi_rsdp;
 unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp);
 #endif
 
-#endif
+#endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 55f6f284e4..d8221a986b 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -19,7 +19,7 @@
  */
 
 #ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
-#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ 1
+#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
 
 /* Chipset types */
 #define HASWELL_MOBILE	0
@@ -233,4 +233,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
 
 #endif
 #endif
-#endif
+#endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */
diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h
index f0e1c537f3..baf12f2a5e 100644
--- a/src/northbridge/intel/nehalem/gma.h
+++ b/src/northbridge/intel/nehalem/gma.h
@@ -19,7 +19,7 @@
  */
 
 #ifndef __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__
-#define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ 1
+#define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__
 
 /* mailbox 0: header */
 typedef struct {
@@ -118,4 +118,4 @@ typedef struct {
 	opregion_vbt_t vbt;
 } __attribute__((packed)) igd_opregion_t;
 
-#endif
+#endif /* __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ */
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 60cafdf275..73137b21e7 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -20,7 +20,7 @@
  */
 
 #ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__
-#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ 1
+#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__
 
 #ifndef __ASSEMBLER__
 
@@ -623,4 +623,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
 
 #endif
 #endif
-#endif
+#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index d38bf0bdc9..0790ae8fd2 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -19,7 +19,7 @@
  */
 
 #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
-#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1
+#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
 
 /* Chipset types */
 #define SANDYBRIDGE_MOBILE	0
@@ -240,4 +240,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion);
 
 #endif
 #endif
-#endif
+#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */
diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h
index 5700842e90..3eb082585d 100644
--- a/src/northbridge/intel/sch/sch.h
+++ b/src/northbridge/intel/sch/sch.h
@@ -20,7 +20,7 @@
  */
 
 #ifndef __SCH_PULSBO_H__
-#define __SCH_PULSBO_H__ 1
+#define __SCH_PULSBO_H__
 
 int sch_port_access_read(int port, int reg, int bytes);
 void sch_port_access_write(int port, int reg, int bytes, long data);
@@ -51,4 +51,4 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
 /* FIXME: should probably be in southbridge, but is setup in romstage, too */
 #define CMC_SHADOW 0x3faf0000
 
-#endif
+#endif /* __SCH_PULSBO_H__ */