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-rw-r--r--src/northbridge/intel/haswell/acpi/hostbridge.asl8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 8fbfabfa71..dd4b79a6cf 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -425,13 +425,17 @@ Method (_CRS, 0, Serialized)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM
- Local0 = ^MCHC.TLUD
+ // Lower 20 bits of TOLUD register need to be masked since they contain lock and
+ // reserved bits.
+ Local0 = ^MCHC.TLUD & (0xfff << 20)
Local1 = ^MCHC.MEBA
// Check if ME base is equal
If (Local0 == Local1) {
// Use Top Of Memory instead
- Local0 = ^MCHC.TOM
+ // Lower 20 bits of TOM register need to be masked since they contain lock and
+ // reserved bits.
+ Local0 = ^MCHC.TOM & (0x7ffff << 20)
}
PMIN = Local0