2 files changed, 28 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index d1d35dbab2..8bf44c1745 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -24,6 +24,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <elog.h>
+#include <cbmem.h>
 #include <pc80/mc146818rtc.h>
 #include "sandybridge.h"
 
@@ -174,3 +175,29 @@ void sandybridge_early_initialization(int chipset_type)
 
 	sandybridge_setup_graphics();
 }
+
+void northbridge_romstage_finalize(int s3resume)
+{
+	MCHBAR16(SSKPD) = 0xCAFE;
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+
+	*(u32 *)CBMEM_BOOT_MODE = 0;
+	*(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+	if (s3resume) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+		if (resume_backup_memory) {
+			*(u32 *)CBMEM_BOOT_MODE = 2;
+			*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+		}
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	} else {
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+	}
+#endif
+}
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 291ea46d8b..d38bf0bdc9 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -209,6 +209,7 @@ void intel_sandybridge_finalize_smm(void);
 int bridge_silicon_revision(void);
 void sandybridge_early_initialization(int chipset_type);
 void sandybridge_late_initialization(void);
+void northbridge_romstage_finalize(int s3resume);
 
 /* debugging functions */
 void print_pci_devices(void);