diff options
Diffstat (limited to 'src/northbridge/intel')
38 files changed, 433 insertions, 433 deletions
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c index 500ea3e138..c116cb6296 100644 --- a/src/northbridge/intel/e7501/debug.c +++ b/src/northbridge/intel/e7501/debug.c @@ -16,8 +16,8 @@ static void print_debug_pci_dev(unsigned dev) static inline void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -35,7 +35,7 @@ static void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); - + for(i = 0; i < 256; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -61,8 +61,8 @@ static void dump_pci_device(unsigned dev) static inline void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0xff, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -104,8 +104,8 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device); #else - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); #endif @@ -141,8 +141,8 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); #else - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); #endif @@ -188,7 +188,7 @@ static inline void dump_smbus_registers(void) print_debug_hex8(device); #endif for(j = 0; j < 256; j++) { - int status; + int status; unsigned char byte; status = smbus_read_byte(device, j); if (status < 0) { @@ -212,10 +212,10 @@ static inline void dump_smbus_registers(void) #endif } print_debug("\n"); - } + } } -static inline void dump_io_resources(unsigned port) +static inline void dump_io_resources(unsigned port) { int i; @@ -257,13 +257,13 @@ static inline void dump_mem(unsigned start, unsigned end) if((i & 0xf)==0) { #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "\n%08x:", i); -#else +#else print_debug("\n"); print_debug_hex32(i); print_debug(":"); #endif } -#if CONFIG_USE_PRINTK_IN_CAR +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i)); #else print_debug(" "); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index c3b373c926..a2e4b245ee 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -112,11 +112,11 @@ static void pci_domain_set_resources(device_t dev) remapbase_r = pci_read_config16(mc_dev, 0xc6); remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00); pci_write_config16(mc_dev, 0xc6, remapbase_r); - + remaplimit_r = pci_read_config16(mc_dev, 0xc8); remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00); pci_write_config16(mc_dev, 0xc8, remaplimit_r); - + /* Report the memory regions */ idx = 10; ram_resource(dev, idx++, 0, 640); @@ -145,7 +145,7 @@ static struct device_operations pci_domain_ops = { .init = 0, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = &pci_cf8_conf1, -}; +}; static void cpu_bus_init(device_t dev) { diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c index 9f757e0f79..ac3bd41866 100644 --- a/src/northbridge/intel/e7501/raminit.c +++ b/src/northbridge/intel/e7501/raminit.c @@ -1,9 +1,9 @@ /* This was originally for the e7500, modified for e7501 - * The primary differences are that 7501 apparently can + * The primary differences are that 7501 apparently can * support single channel RAM (i haven't tested), * CAS1.5 is no longer supported, The ECC scrubber * now supports a mode to zero RAM and init ECC in one step - * and the undocumented registers at 0x80 require new + * and the undocumented registers at 0x80 require new * (undocumented) values determined by guesswork and * comparison w/ OEM BIOS values. * Steven James 02/06/2003 @@ -17,7 +17,7 @@ #include <stdlib.h> #include "e7501.h" -// Uncomment this to enable run-time checking of DIMM parameters +// Uncomment this to enable run-time checking of DIMM parameters // for dual-channel operation // Unfortunately the code seems to chew up several K of space. //#define VALIDATE_DIMM_COMPATIBILITY @@ -52,10 +52,10 @@ struct dimm_size { /**********************************************************************************/ static const uint32_t refresh_frequency[] = { - /* Relative frequency (array value) of each E7501 Refresh Mode Select + /* Relative frequency (array value) of each E7501 Refresh Mode Select * (RMS) value (array index) * 0 == least frequent refresh (longest interval between refreshes) - * [0] disabled -> 0 + * [0] disabled -> 0 * [1] 15.6 usec -> 2 * [2] 7.8 usec -> 3 * [3] 64 usec -> 1 @@ -68,10 +68,10 @@ static const uint32_t refresh_frequency[] = { }; static const uint32_t refresh_rate_map[] = { - /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode + /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode * Select values (array value) * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 - * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and + * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and * 64 clock (481 ns) (7) refresh. * [0] == 15.625 us -> 15.6 us * [1] == 3.9 us -> 481 ns @@ -110,7 +110,7 @@ static const long constant_register_values[] = { */ // Not everyone wants to be Super Micro Computer, Inc. // The mainboard should set this if desired. - // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), + // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), /* Undocumented * (DRAM Read Timing Control, if similar to 855PM?) @@ -125,11 +125,11 @@ static const long constant_register_values[] = { * CAS 2.0 values taken from Intel BIOS settings, others are a guess * and may be terribly wrong. Old values preserved as comments until I * figure this out for sure. - * e7501 docs claim that CAS1.5 is unsupported, so it may or may not + * e7501 docs claim that CAS1.5 is unsupported, so it may or may not * work at all. * Steven James 02/06/2003 */ - /* NOTE: values now configured in configure_e7501_cas_latency() based + /* NOTE: values now configured in configure_e7501_cas_latency() based * on SPD info and total number of DIMMs (per Intel) */ @@ -168,8 +168,8 @@ static const long constant_register_values[] = { /* DRB - DRAM Row Boundary Registers * 0x60 - 0x6F * An array of 8 byte registers, which hold the ending - * memory address assigned to each pair of DIMMS, in 64MB - * granularity. + * memory address assigned to each pair of DIMMS, in 64MB + * granularity. */ // Conservatively say each row has 64MB of ram, we will fix this up later // NOTE: These defaults allow us to prime all of the DIMMs on the board @@ -178,7 +178,7 @@ static const long constant_register_values[] = { 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24), 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24), - /* DRA - DRAM Row Attribute Register + /* DRA - DRAM Row Attribute Register * 0x70 Row 0,1 * 0x71 Row 2,3 * 0x72 Row 4,5 @@ -312,7 +312,7 @@ static const long constant_register_values[] = { // .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), // .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8), - // Default to dual-channel mode, ECC, 1-clock address/cmd hold + // Default to dual-channel mode, ECC, 1-clock address/cmd hold // NOTE: configure_e7501_dram_controller_mode() configures further 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8), @@ -425,7 +425,7 @@ static const long constant_register_values[] = { 0xf4, 0x3f8ffffd, 0x40300002, #ifdef SUSPICIOUS_LOOKING_CODE - // SJM: Undocumented. + // SJM: Undocumented. // This will access D2:F0:0x50, is this correct?? 0x1050, 0xffffffcf, 0x00000030, #endif @@ -606,11 +606,11 @@ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) // Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate // Return Value: dimm_size - log2(number of bits) for each side of the DIMM // Description: Calculate the log base 2 size in bits of both DIMM sides. -// log2(# bits) = (# columns) + log2(data width) + +// log2(# bits) = (# columns) + log2(data width) + // (# rows) + log2(banks per SDRAM) // -// Note that it might be easier to use SPD byte 31 here, it has the -// DIMM size as a multiple of 4MB. The way we do it now we can size +// Note that it might be easier to use SPD byte 31 here, it has the +// DIMM size as a multiple of 4MB. The way we do it now we can size // both sides of an asymmetric dimm. // static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) @@ -653,7 +653,7 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) #ifdef VALIDATE_DIMM_COMPATIBILITY //---------------------------------------------------------------------------------- // Function: are_spd_values_equal -// Parameters: spd_byte_number - +// Parameters: spd_byte_number - // dimmN_address - SMBus addresses of DIMM sockets to interrogate // Return Value: 1 if both DIMM sockets report the same value for the specified // SPD parameter; 0 if the values differed or an error occurred. @@ -834,7 +834,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) //---------------------------------------------------------------------------------- // Function: do_ram_command -// Parameters: +// Parameters: // command - specifies the command to be sent to the DIMMs: // RAM_COMMAND_NOP - No Operation // RAM_COMMAND_PRECHARGE - Precharge all banks @@ -860,7 +860,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) dram_controller_mode |= command; pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - // RAM_COMMAND_NORMAL is an exception. + // RAM_COMMAND_NORMAL is an exception. // It affects only the memory controller and does not need to be "sent" to the DIMMs. if (command != RAM_COMMAND_NORMAL) { @@ -897,7 +897,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) // NOTE: 0x40 * 64 MB == 4 GB ASSERT(dimm_start_64M_multiple < 0x40); - // NOTE: 2^26 == 64 MB + // NOTE: 2^26 == 64 MB uint32_t dimm_start_address = dimm_start_64M_multiple << 26; @@ -921,7 +921,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) // Parameters: jedec_mode_bits - for mode register set & extended mode register set // commands, bits 0-12 contain the register value in JEDEC format. // Return Value: None -// Description: Set the mode register of all DIMMs. The proper CAS# latency +// Description: Set the mode register of all DIMMs. The proper CAS# latency // setting is added to the mode bits specified by the caller. // static void set_ram_mode(uint16_t jedec_mode_bits) @@ -954,11 +954,11 @@ static void set_ram_mode(uint16_t jedec_mode_bits) //---------------------------------------------------------------------------------- // Function: configure_dimm_row_boundaries -// Parameters: +// Parameters: // dimm_log2_num_bits - log2(number of bits) for each side of the DIMM -// total_dram_64M_multiple - total DRAM in the system (as a +// total_dram_64M_multiple - total DRAM in the system (as a // multiple of 64 MB) for DIMMs < dimm_index -// dimm_index - which DIMM pair is being processed +// dimm_index - which DIMM pair is being processed // (0..MAX_DIMM_SOCKETS_PER_CHANNEL) // Return Value: New multiple of 64 MB total DRAM in the system // Description: Configure the E7501's DRAM Row Boundary registers for the memory @@ -975,7 +975,7 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits ASSERT((dimm_log2_num_bits.side2 == 0) || (dimm_log2_num_bits.side2 >= 28)); - // In dual-channel mode, we are called only once for each pair of DIMMs. + // In dual-channel mode, we are called only once for each pair of DIMMs. // Each time we process twice the capacity of a single DIMM. // Convert single DIMM capacity to paired DIMM capacity @@ -994,7 +994,7 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1), total_dram_64M_multiple); - // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair + // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair // (as a multiple of 64 MB) to the total capacity of the system if (dimm_log2_num_bits.side2 >= 29) total_dram_64M_multiple += @@ -1021,12 +1021,12 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits // Function: configure_e7501_ram_addresses // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None -// Description: Program the E7501's DRAM row boundary addresses and its Top Of -// Low Memory (TOLM). If necessary, set up a remap window so we -// don't waste DRAM that ordinarily would lie behind addresses +// Description: Program the E7501's DRAM row boundary addresses and its Top Of +// Low Memory (TOLM). If necessary, set up a remap window so we +// don't waste DRAM that ordinarily would lie behind addresses // reserved for memory-mapped I/O. // static void configure_e7501_ram_addresses(const struct mem_controller @@ -1181,11 +1181,11 @@ static void initialize_ecc(void) // Function: configure_e7501_dram_timing // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None -// Description: Program the DRAM Timing register of the E7501 (except for CAS# -// latency, which is assumed to have been programmed already), based +// Description: Program the DRAM Timing register of the E7501 (except for CAS# +// latency, which is assumed to have been programmed already), based // on the parameters of the various installed DIMMs. // static void configure_e7501_dram_timing(const struct mem_controller *ctrl, @@ -1255,7 +1255,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, if (slowest_row_precharge > ((22 << 2) | (2 << 0))) die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks else if (slowest_row_precharge > (15 << 2)) - dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks + dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks else dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks @@ -1267,7 +1267,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0))) die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks else if (slowest_ras_cas_delay > (15 << 2)) - dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks + dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks else dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks @@ -1280,7 +1280,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, if (slowest_active_to_precharge_delay > 52) die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks else if (slowest_active_to_precharge_delay > 45) - dram_timing |= (0 << 9); // 46-52 ns: 7 clocks + dram_timing |= (0 << 9); // 46-52 ns: 7 clocks else if (slowest_active_to_precharge_delay > 37) dram_timing |= (1 << 9); // 38-45 ns: 6 clocks else @@ -1318,7 +1318,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, // Function: configure_e7501_cas_latency // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Determine the shortest CAS# latency that the E7501 and all DIMMs @@ -1475,7 +1475,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, // Function: configure_e7501_dram_controller_mode // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Configure the refresh interval so that we refresh no more often @@ -1583,7 +1583,7 @@ static void configure_e7501_dram_controller_mode(const struct // Function: configure_e7501_row_attributes // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see +// dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Configure the E7501's DRAM Row Attributes (DRA) registers @@ -1636,7 +1636,7 @@ static void configure_e7501_row_attributes(const struct mem_controller //---------------------------------------------------------------------------------- // Function: enable_e7501_clocks -// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see +// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see // spd_get_supported_dimms() // Return Value: None // Description: Enable clock signals for populated DIMM sockets and disable them @@ -1690,8 +1690,8 @@ static void RAM_RESET_DDR_PTR(void) // Description: Set E7501 registers that are either independent of DIMM specifics, // or establish default settings that will be overridden when we // learn the specifics. -// This sets PCI configuration registers to known good values based -// on the table 'constant_register_values', which are a triple of +// This sets PCI configuration registers to known good values based +// on the table 'constant_register_values', which are a triple of // configuration register offset, mask, and bits to set. // static void ram_set_d0f0_regs(void) @@ -1748,8 +1748,8 @@ static void write_8dwords(const uint32_t * src_addr, uint32_t dst_addr) // Parameters: None // Return Value: None // Description: Set the E7501's (undocumented) RCOMP registers. -// Per the 855PM datasheet and IXP2800 HW Initialization Reference -// Manual, RCOMP registers appear to affect drive strength, +// Per the 855PM datasheet and IXP2800 HW Initialization Reference +// Manual, RCOMP registers appear to affect drive strength, // pullup/pulldown offset, and slew rate of various signal groups. // Comments below are conjecture based on apparent similarity // between the E7501 and these two chips. @@ -1980,9 +1980,9 @@ static void sdram_enable(int controllers, // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard // Return Value: None -// Description: Configure SDRAM controller parameters that depend on -// characteristics of the DIMMs installed in the system. These -// characteristics are read from the DIMMs via the standard Serial +// Description: Configure SDRAM controller parameters that depend on +// characteristics of the DIMMs installed in the system. These +// characteristics are read from the DIMMs via the standard Serial // Presence Detect (SPD) interface. // static void sdram_set_spd_registers(const struct mem_controller *ctrl) @@ -2011,7 +2011,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) } /* NOTE: configure_e7501_ram_addresses() is NOT called here. - * We want to keep the default 64 MB/row mapping until sdram_enable() is called, + * We want to keep the default 64 MB/row mapping until sdram_enable() is called, * even though the default mapping is almost certainly incorrect. * The default mapping makes it easy to initialize all of the DIMMs * even if the total system memory is > 4 GB. @@ -2028,7 +2028,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) // Parameters: ctrl - PCI addresses of memory controller functions, and // SMBus addresses of DIMM slots on the mainboard // Return Value: None -// Description: Do basic ram setup that does NOT depend on serial presence detect +// Description: Do basic ram setup that does NOT depend on serial presence detect // information (i.e. independent of DIMM specifics). // static void sdram_set_registers(const struct mem_controller *ctrl) diff --git a/src/northbridge/intel/e7501/raminit.h b/src/northbridge/intel/e7501/raminit.h index 0d09414904..df0e9291a3 100644 --- a/src/northbridge/intel/e7501/raminit.h +++ b/src/northbridge/intel/e7501/raminit.h @@ -6,12 +6,12 @@ #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) struct mem_controller { - device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller + device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller // SMBus addresses of DIMM slots for each channel, // in order from closest to MCH to furthest away // 0 == not present - uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL]; + uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL]; uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; }; diff --git a/src/northbridge/intel/e7501/reset_test.c b/src/northbridge/intel/e7501/reset_test.c index 79a5cdaee1..1c0dad5ed9 100644 --- a/src/northbridge/intel/e7501/reset_test.c +++ b/src/northbridge/intel/e7501/reset_test.c @@ -7,12 +7,12 @@ */ static int bios_reset_detected(void) { uint32_t dword; - + dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - + if( (dword & DRC_DONE) != 0 ) { return 1; - } - + } + return 0; } diff --git a/src/northbridge/intel/e7520/memory_initialized.c b/src/northbridge/intel/e7520/memory_initialized.c index 133d1c4f88..d7a8048567 100644 --- a/src/northbridge/intel/e7520/memory_initialized.c +++ b/src/northbridge/intel/e7520/memory_initialized.c @@ -10,4 +10,4 @@ static inline int memory_initialized(void) //print_debug("\n"); return (drc & (1<<29)); -} +} diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index efb7f0263b..93604b6cf7 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -16,7 +16,7 @@ static unsigned int max_bus; -static void ram_resource(device_t dev, unsigned long index, +static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { struct resource *resource; @@ -195,7 +195,7 @@ static void mc_set_resources(device_t dev) static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/northbridge/intel/e7520/pciexp_porta.c b/src/northbridge/intel/e7520/pciexp_porta.c index 07440e368e..ab73a713c2 100644 --- a/src/northbridge/intel/e7520/pciexp_porta.c +++ b/src/northbridge/intel/e7520/pciexp_porta.c @@ -7,16 +7,16 @@ #include <arch/io.h> #include "chip.h" #include <reset.h> - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -58,5 +58,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA, }; - + diff --git a/src/northbridge/intel/e7520/pciexp_porta1.c b/src/northbridge/intel/e7520/pciexp_porta1.c index 26605df8ab..c79535fbb0 100644 --- a/src/northbridge/intel/e7520/pciexp_porta1.c +++ b/src/northbridge/intel/e7520/pciexp_porta1.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA1, }; - + diff --git a/src/northbridge/intel/e7520/pciexp_portb.c b/src/northbridge/intel/e7520/pciexp_portb.c index 668c665988..b20abdee6f 100644 --- a/src/northbridge/intel/e7520/pciexp_portb.c +++ b/src/northbridge/intel/e7520/pciexp_portb.c @@ -7,16 +7,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -38,5 +38,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PB, }; - + diff --git a/src/northbridge/intel/e7520/pciexp_portc.c b/src/northbridge/intel/e7520/pciexp_portc.c index fe55e661ec..d2706d1364 100644 --- a/src/northbridge/intel/e7520/pciexp_portc.c +++ b/src/northbridge/intel/e7520/pciexp_portc.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7520_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PC, }; - + diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index 836e6f8c7c..7f1b9d500a 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -33,13 +33,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl) /* CKDIS 0x8c disable clocks */ PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - /* 0x9c Device present and extended RAM control + /* 0x9c Device present and extended RAM control * DEVPRES is very touchy, hard code the initialization * of PCI-E ports here. */ PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG, - /* 0xc8 Remap RAM base and limit off */ + /* 0xc8 Remap RAM base and limit off */ PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000, /* ??? */ @@ -57,7 +57,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG, /* 0x14 */ - PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, + PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, }; int i; int max; @@ -122,7 +122,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - + low = spd_read_byte(device, 6); /* (low byte) */ if (low < 0) goto hw_err; value = value | (low & 0xff); @@ -169,7 +169,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask) { int i; int cum; - + for(i = cum = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; if (dimm_mask & (1 << i)) { @@ -233,7 +233,7 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) } -static int spd_set_row_attributes(const struct mem_controller *ctrl, +static int spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) { @@ -264,22 +264,22 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, reg += log2(value & 0xff); /* Get the device width and convert it to a power of two */ - value = spd_read_byte(ctrl->channel0[cnt], 13); + value = spd_read_byte(ctrl->channel0[cnt], 13); if (value < 0) goto hw_err; value = log2(value & 0xff); reg += value; if(reg < 27) goto hw_err; reg -= 27; reg += (value << 2); - + dra += reg << (cnt*8); value = spd_read_byte(ctrl->channel0[cnt], 5); if (value & 2) - dra += reg << ((cnt*8)+4); + dra += reg << ((cnt*8)+4); } /* 0x70 DRA */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra); goto out; val_err: @@ -293,7 +293,7 @@ hw_err: } -static int spd_set_drt_attributes(const struct mem_controller *ctrl, +static int spd_set_drt_attributes(const struct mem_controller *ctrl, long dimm_mask, uint32_t drc) { int value; @@ -305,23 +305,23 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, int latency; uint32_t index = 0; uint32_t index2 = 0; - static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; + static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; static const int latency_indicies[] = { 26, 23, 9 }; /* 0x78 DRT */ drt = pci_read_config32(PCI_DEV(0, 0x00, 0), DRT); drt &= 3; /* save bits 1:0 */ - + for(first_dimm = 0; first_dimm < 4; first_dimm++) { - if (dimm_mask & (1 << first_dimm)) + if (dimm_mask & (1 << first_dimm)) break; } - + /* get dimm type */ value = spd_read_byte(ctrl->channel0[first_dimm], 2); if(value == 8) { drt |= (3<<5); /* back to bark write turn around & cycle add */ - } + } drt |= (3<<18); /* Trasmax */ @@ -332,22 +332,22 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */ /* Compute the lowest cas latency supported */ latency = log2(reg) -2; - + /* Loop through and find a fast clock with a low latency */ for(index = 0; index < 3; index++, latency++) { if ((latency < 2) || (latency > 4) || (!(reg & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[cnt], + value = spd_read_byte(ctrl->channel0[cnt], latency_indicies[index]); - + if(value <= cycle_time[drc&3]) { if( latency > cas_latency) { cas_latency = latency; } break; - } + } } } index = (cas_latency-2); @@ -401,7 +401,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x03c) { drt |= (0<<10); @@ -411,7 +411,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, /* Tdal Write auto precharge recovery delay */ drt |= (1<<12); - + /* Trc TRS min */ if((index2&0x0ff00)<=0x03700) drt |= (0<<14); @@ -419,9 +419,9 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, drt |= (1<<14); else drt |= (2<<14); /* spd 41 */ - + drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0140000) { drt |= (0<<20); @@ -432,7 +432,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (3<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -446,14 +446,14 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else if(value <= 0x60) { /* 167 Mhz */ /* according to new documentation CAS latency is 00 - * for bits 3:2 for all 167 Mhz + * for bits 3:2 for all 167 Mhz drt |= ((index&3)<<2); */ /* set CAS latency */ if((index&0x0ff00)<=0x03000) { drt |= (1<<8); /* Trp RAS Precharg */ } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x030) { drt |= (0<<10); @@ -462,13 +462,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (2<<12); - + drt |= (2<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (2<<16); /* Twr not defined for DDR docs say 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0180000) { drt |= (0<<20); @@ -477,7 +477,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x0480000) { drt |= (0<<22); @@ -505,13 +505,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); - + drt |= (1<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (1<<16); /* Twr not defined for DDR docs say 1 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x01e0000) { drt |= (0<<20); @@ -520,7 +520,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -529,13 +529,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<22); } - + /* Based on CAS latency */ if(index&7) drt |= (0x099<<24); else drt |= (0x055<<24); - + } else { die("Invalid SPD 9 bus speed.\n"); @@ -547,7 +547,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, return(cas_latency); } -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, +static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, long dimm_mask) { int value; @@ -558,12 +558,12 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, unsigned char dram_type = 0xff; unsigned char ecc = 0xff; unsigned char rate = 62; - static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; + static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; static const unsigned char drc_rates[5] = {0,15,7,62,3}; static const unsigned char fsb_conversion[4] = {3,1,3,2}; /* 0x7c DRC */ - drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC); + drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC); for(cnt=0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; @@ -578,7 +578,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if (ecc == 1) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else if ( reg == 7 ) { if ( ecc == 0xff) { ecc = 1; @@ -586,7 +586,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if ( ecc > 1 ) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else { die("ERROR - RAM not DDR\n"); } @@ -650,7 +650,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, drc |= (fsb_conversion[value] << 2); drc &= ~(3 << 0); /* set the dram type */ drc |= (dram_type << 0); - + goto out; val_err: @@ -662,7 +662,7 @@ hw_err: return drc; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { long dimm_mask; @@ -681,7 +681,7 @@ static void do_delay(void) unsigned char b; for(i=0;i<16;i++) b=inb(0x80); -} +} static void pll_setup(uint32_t drc) { @@ -710,7 +710,7 @@ static void pll_setup(uint32_t drc) } mainboard_set_e7520_pll(pins); return; -} +} #define TIMEOUT_LOOPS 300000 @@ -724,7 +724,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) unsigned int dimm,i; unsigned int data32; unsigned int t4; - + /* Set up northbridge values */ /* ODT enable */ pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xf0000180); @@ -741,10 +741,10 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) for(i=0;i<1;i++) { if((t4&0x0f) == 1) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00000010; /* EEES */ + data32 = 0x00000010; /* EEES */ break; } - if ( ((t4>>16)&0x0f) == 0 ) { + if ( ((t4>>16)&0x0f) == 0 ) { data32 = 0x00003132; /* EESS */ break; } @@ -757,7 +757,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) } if((t4&0x0f) == 2) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00003132; /* EEED */ + data32 = 0x00003132; /* EEED */ break; } if ( ((t4>>8)&0x0f) == 2 ) { @@ -784,14 +784,14 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, 0x83000003 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) break; } } -} +} static void set_receive_enable(const struct mem_controller *ctrl) { unsigned int i; @@ -799,7 +799,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) uint32_t recena=0; uint32_t recenb=0; - { + { unsigned int dimm; unsigned int edge; int32_t data32; @@ -817,7 +817,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) if(!(dimm&1)) { write32(BAR+DCALDATA+(17*4), 0x04020000); write32(BAR+DCALCSR, 0x83800004 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) @@ -825,7 +825,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) } if(i>=1000) continue; - + dcal_data32_0 = read32(BAR+DCALDATA + 0); dcal_data32_1 = read32(BAR+DCALDATA + 4); dcal_data32_2 = read32(BAR+DCALDATA + 8); @@ -914,7 +914,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) data32++; } /* test for frame edge cross overs */ - if((edge == 1) && (data32 > 12) && + if((edge == 1) && (data32 > 12) && (((recen+16)-data32) < 3)) { data32 = 0; cnt += 2; @@ -1063,15 +1063,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* FSB 200 DIMM 400 */ {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}}, }; - + static const uint32_t dqs_data[] = { - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); @@ -1101,24 +1101,24 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* 0x7c DRC */ pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); - + /* turn the clocks on */ /* 0x8c CKDIS */ pci_write_config16(PCI_DEV(0, 0x00, 0), CKDIS, 0x0000); - + /* 0x9a DDRCSR Take subsystem out of idle */ data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DDRCSR); data16 &= ~(7 << 12); data16 |= (3 << 12); /* use dual channel lock step */ pci_write_config16(PCI_DEV(0, 0x00, 0), DDRCSR, data16); - + /* program row size DRB */ spd_set_ram_size(ctrl, mask); /* program page size DRA */ spd_set_row_attributes(ctrl, mask); - /* program DRT timing values */ + /* program DRT timing values */ cas_latency = spd_set_drt_attributes(ctrl, mask, drc); for(i=0;i<8;i++) { /* loop throught each dimm to test for row */ @@ -1127,7 +1127,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); /* Apply NOP */ do_delay(); - + write32(BAR + 0x100, (0x03000000 | (i<<20))); write32(BAR+0x100, (0x83000000 | (i<<20))); @@ -1137,12 +1137,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 = read32(BAR+DCALCSR); } - + /* Apply NOP */ do_delay(); - for(cs=0;cs<8;cs++) { - write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); + for(cs=0;cs<8;cs++) { + write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); @@ -1150,7 +1150,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharg all banks */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1160,10 +1160,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* EMRS dll's enabled */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ /* fixme hard code AL additive latency */ write32(BAR+DCALADDR, 0x0b940001); @@ -1188,7 +1188,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* CAS Latency 2.5 */ mode_reg = 0x016a0000; } - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1200,7 +1200,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) do_delay(); do_delay(); do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1210,17 +1210,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Do 2 refreshes */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) @@ -1228,33 +1228,33 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } do_delay(); /* for good luck do 6 more */ - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); /* MRS reset dll's normal */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1279,7 +1279,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+DCALCSR, 0x0000000f); /* DDR1 This is test code to copy some codes in the factory setup */ - + write32(BAR, 0x00100000); if ((drc & 3) == 2) { /* DDR2 */ @@ -1292,9 +1292,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* receive enable calibration */ set_receive_enable(ctrl); - + /* DQS */ - pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 ); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 ); for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) { write32(cnt, dqs_data[i]); } @@ -1303,7 +1303,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Enable refresh */ /* 0x7c DRC */ data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ @@ -1311,7 +1311,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(i=0;i<64;i+=4) { write32(BAR+DCALDATA+i, 0x00000000); } - + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1331,22 +1331,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) break; } print_debug("Done\n"); - + /* Set initialization complete */ /* 0x7c DRC */ drc |= (1 << 29); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); /* Set the ecc mode */ - pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc); /* Enable memory scrubbing */ - /* 0x52 MCHSCRB */ + /* 0x52 MCHSCRB */ data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), MCHSCRB); data16 &= ~0x0f; data16 |= ((2 << 2) | (2 << 0)); - pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16); + pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16); /* The memory is now setup, use it */ cache_lbmem(MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/e7525/memory_initialized.c b/src/northbridge/intel/e7525/memory_initialized.c index 6eb31a8ca3..69bfdf32dd 100644 --- a/src/northbridge/intel/e7525/memory_initialized.c +++ b/src/northbridge/intel/e7525/memory_initialized.c @@ -6,4 +6,4 @@ static inline int memory_initialized(void) uint32_t drc; drc = pci_read_config32(NB_DEV, DRC); return (drc & (1<<29)); -} +} diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 02bf119b96..559dc15b8b 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -16,7 +16,7 @@ static unsigned int max_bus; -static void ram_resource(device_t dev, unsigned long index, +static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { struct resource *resource; @@ -195,7 +195,7 @@ static void mc_set_resources(device_t dev) static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } diff --git a/src/northbridge/intel/e7525/pciexp_porta.c b/src/northbridge/intel/e7525/pciexp_porta.c index 3efc378ce0..4bae287df4 100644 --- a/src/northbridge/intel/e7525/pciexp_porta.c +++ b/src/northbridge/intel/e7525/pciexp_porta.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA, }; - + diff --git a/src/northbridge/intel/e7525/pciexp_porta1.c b/src/northbridge/intel/e7525/pciexp_porta1.c index 4f4204b7ad..b54ee8add6 100644 --- a/src/northbridge/intel/e7525/pciexp_porta1.c +++ b/src/northbridge/intel/e7525/pciexp_porta1.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PA1, }; - + diff --git a/src/northbridge/intel/e7525/pciexp_portb.c b/src/northbridge/intel/e7525/pciexp_portb.c index faf34dcfae..7b78b42e07 100644 --- a/src/northbridge/intel/e7525/pciexp_portb.c +++ b/src/northbridge/intel/e7525/pciexp_portb.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PB, }; - + diff --git a/src/northbridge/intel/e7525/pciexp_portc.c b/src/northbridge/intel/e7525/pciexp_portc.c index d7d75a2f9c..da6eaf70de 100644 --- a/src/northbridge/intel/e7525/pciexp_portc.c +++ b/src/northbridge/intel/e7525/pciexp_portc.c @@ -6,16 +6,16 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" - + typedef struct northbridge_intel_e7525_config config_t; static void pcie_init(struct device *dev) { config_t *config; - + /* Get the chip configuration */ config = dev->chip_info; - + if(config->intrline) { pci_write_config32(dev, 0x3c, config->intrline); } @@ -37,5 +37,5 @@ static const struct pci_driver pci_driver __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_PCIE_PC, }; - + diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c index 0d18022020..be44434bf5 100644 --- a/src/northbridge/intel/e7525/raminit.c +++ b/src/northbridge/intel/e7525/raminit.c @@ -33,13 +33,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl) /* CKDIS 0x8c disable clocks */ PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, - /* 0x9c Device present and extended RAM control + /* 0x9c Device present and extended RAM control * DEVPRES is very touchy, hard code the initialization * of PCI-E ports here. */ PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG, - /* 0xc8 Remap RAM base and limit off */ + /* 0xc8 Remap RAM base and limit off */ PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000, /* ??? */ @@ -57,7 +57,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG, /* 0x14 */ - PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, + PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, BAR |0, }; int i; int max; @@ -122,7 +122,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device) if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - + low = spd_read_byte(device, 6); /* (low byte) */ if (low < 0) goto hw_err; value = value | (low & 0xff); @@ -169,7 +169,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask) { int i; int cum; - + for(i = cum = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; if (dimm_mask & (1 << i)) { @@ -233,7 +233,7 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) } -static int spd_set_row_attributes(const struct mem_controller *ctrl, +static int spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_mask) { @@ -264,22 +264,22 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, reg += log2(value & 0xff); /* Get the device width and convert it to a power of two */ - value = spd_read_byte(ctrl->channel0[cnt], 13); + value = spd_read_byte(ctrl->channel0[cnt], 13); if (value < 0) goto hw_err; value = log2(value & 0xff); reg += value; if(reg < 27) goto hw_err; reg -= 27; reg += (value << 2); - + dra += reg << (cnt*8); value = spd_read_byte(ctrl->channel0[cnt], 5); if (value & 2) - dra += reg << ((cnt*8)+4); + dra += reg << ((cnt*8)+4); } /* 0x70 DRA */ - pci_write_config32(ctrl->f0, DRA, dra); + pci_write_config32(ctrl->f0, DRA, dra); goto out; val_err: @@ -293,7 +293,7 @@ hw_err: } -static int spd_set_drt_attributes(const struct mem_controller *ctrl, +static int spd_set_drt_attributes(const struct mem_controller *ctrl, long dimm_mask, uint32_t drc) { int value; @@ -305,23 +305,23 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, int latency; uint32_t index = 0; uint32_t index2 = 0; - static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; + static const unsigned char cycle_time[3] = {0x75,0x60,0x50}; static const int latency_indicies[] = { 26, 23, 9 }; /* 0x78 DRT */ drt = pci_read_config32(ctrl->f0, DRT); drt &= 3; /* save bits 1:0 */ - + for(first_dimm = 0; first_dimm < 4; first_dimm++) { - if (dimm_mask & (1 << first_dimm)) + if (dimm_mask & (1 << first_dimm)) break; } - + /* get dimm type */ value = spd_read_byte(ctrl->channel0[first_dimm], 2); if(value == 8) { drt |= (3<<5); /* back to bark write turn around & cycle add */ - } + } drt |= (3<<18); /* Trasmax */ @@ -332,22 +332,22 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, reg = spd_read_byte(ctrl->channel0[cnt], 18); /* CAS Latency */ /* Compute the lowest cas latency supported */ latency = log2(reg) -2; - + /* Loop through and find a fast clock with a low latency */ for(index = 0; index < 3; index++, latency++) { if ((latency < 2) || (latency > 4) || (!(reg & (1 << latency)))) { continue; } - value = spd_read_byte(ctrl->channel0[cnt], + value = spd_read_byte(ctrl->channel0[cnt], latency_indicies[index]); - + if(value <= cycle_time[drc&3]) { if( latency > cas_latency) { cas_latency = latency; } break; - } + } } } index = (cas_latency-2); @@ -401,7 +401,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x03c) { drt |= (0<<10); @@ -411,7 +411,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, /* Tdal Write auto precharge recovery delay */ drt |= (1<<12); - + /* Trc TRS min */ if((index2&0x0ff00)<=0x03700) drt |= (0<<14); @@ -419,9 +419,9 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, drt |= (1<<14); else drt |= (2<<14); /* spd 41 */ - + drt |= (2<<16); /* Twr not defined for DDR docs say use 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0140000) { drt |= (0<<20); @@ -432,7 +432,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (3<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -446,14 +446,14 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else if(value <= 0x60) { /* 167 Mhz */ /* according to new documentation CAS latency is 00 - * for bits 3:2 for all 167 Mhz + * for bits 3:2 for all 167 Mhz drt |= ((index&3)<<2); */ /* set CAS latency */ if((index&0x0ff00)<=0x03000) { drt |= (1<<8); /* Trp RAS Precharg */ } else { drt |= (2<<8); /* Trp RAS Precharg */ } - + /* Trcd RAS to CAS delay */ if((index2&0x0ff)<=0x030) { drt |= (0<<10); @@ -462,13 +462,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (2<<12); - + drt |= (2<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (2<<16); /* Twr not defined for DDR docs say 2 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x0180000) { drt |= (0<<20); @@ -477,7 +477,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x0480000) { drt |= (0<<22); @@ -505,13 +505,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* Tdal Write auto precharge recovery delay */ - drt |= (1<<12); - + drt |= (1<<12); + /* Trc TRS min */ drt |= (2<<14); /* spd 41, but only one choice */ - + drt |= (1<<16); /* Twr not defined for DDR docs say 1 */ - + /* Trrd Row Delay */ if((index&0x0ff0000)<=0x01e0000) { drt |= (0<<20); @@ -520,7 +520,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<20); } - + /* Trfc Auto refresh cycle time */ if((index2&0x0ff0000)<=0x04b0000) { drt |= (0<<22); @@ -529,13 +529,13 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } else { drt |= (2<<22); } - + /* Based on CAS latency */ if(index&7) drt |= (0x099<<24); else drt |= (0x055<<24); - + } else { die("Invalid SPD 9 bus speed.\n"); @@ -547,7 +547,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, return(cas_latency); } -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, +static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, long dimm_mask) { int value; @@ -558,12 +558,12 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, unsigned char dram_type = 0xff; unsigned char ecc = 0xff; unsigned char rate = 62; - static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; + static const unsigned char spd_rates[6] = {15,3,7,7,62,62}; static const unsigned char drc_rates[5] = {0,15,7,62,3}; static const unsigned char fsb_conversion[4] = {3,1,3,2}; /* 0x7c DRC */ - drc = pci_read_config32(ctrl->f0, DRC); + drc = pci_read_config32(ctrl->f0, DRC); for(cnt=0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; @@ -578,7 +578,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if (ecc == 1) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else if ( reg == 7 ) { if ( ecc == 0xff) { ecc = 1; @@ -586,7 +586,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, else if ( ecc > 1 ) { die("ERROR - Mixed DDR & DDR2 RAM\n"); } - } + } else { die("ERROR - RAM not DDR\n"); } @@ -650,7 +650,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, drc |= (fsb_conversion[value] << 2); drc &= ~(3 << 0); /* set the dram type */ drc |= (dram_type << 0); - + goto out; val_err: @@ -662,7 +662,7 @@ hw_err: return drc; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { long dimm_mask; @@ -681,7 +681,7 @@ static void do_delay(void) unsigned char b; for(i=0;i<16;i++) b=inb(0x80); -} +} #define TIMEOUT_LOOPS 300000 @@ -695,7 +695,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) unsigned int dimm,i; unsigned int data32; unsigned int t4; - + /* Set up northbridge values */ /* ODT enable */ pci_write_config32(ctrl->f0, 0x88, 0xf0000180); @@ -712,10 +712,10 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) for(i=0;i<1;i++) { if((t4&0x0f) == 1) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00000010; /* EEES */ + data32 = 0x00000010; /* EEES */ break; } - if ( ((t4>>16)&0x0f) == 0 ) { + if ( ((t4>>16)&0x0f) == 0 ) { data32 = 0x00003132; /* EESS */ break; } @@ -728,7 +728,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) } if((t4&0x0f) == 2) { if( ((t4>>8)&0x0f) == 0 ) { - data32 = 0x00003132; /* EEED */ + data32 = 0x00003132; /* EEED */ break; } if ( ((t4>>8)&0x0f) == 2 ) { @@ -755,14 +755,14 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) write32(BAR+DCALADDR, 0x0b840001); write32(BAR+DCALCSR, 0x83000003 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) break; } } -} +} static void set_receive_enable(const struct mem_controller *ctrl) { unsigned int i; @@ -770,7 +770,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) uint32_t recena=0; uint32_t recenb=0; - { + { unsigned int dimm; unsigned int edge; int32_t data32; @@ -788,7 +788,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) if(!(dimm&1)) { write32(BAR+DCALDATA+(17*4), 0x04020000); write32(BAR+DCALCSR, 0x83800004 | (dimm << 20)); - + for(i=0;i<1001;i++) { data32 = read32(BAR+DCALCSR); if(!(data32 & (1<<31))) @@ -796,7 +796,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) } if(i>=1000) continue; - + dcal_data32_0 = read32(BAR+DCALDATA + 0); dcal_data32_1 = read32(BAR+DCALDATA + 4); dcal_data32_2 = read32(BAR+DCALDATA + 8); @@ -883,7 +883,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) data32++; } /* test for frame edge cross overs */ - if((edge == 1) && (data32 > 12) && + if((edge == 1) && (data32 > 12) && (((recen+16)-data32) < 3)) { data32 = 0; cnt += 2; @@ -1034,15 +1034,15 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* FSB 200 DIMM 400 */ {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}}, }; - + static const uint32_t dqs_data[] = { - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, - 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, + 0xffffffff, 0xffffffff, 0x000000ff, 0xffffffff, 0xffffffff, 0x000000ff}; mask = spd_detect_dimms(ctrl); @@ -1071,24 +1071,24 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* 0x7c DRC */ pci_write_config32(ctrl->f0, DRC, data32); - + /* turn the clocks on */ /* 0x8c CKDIS */ pci_write_config16(ctrl->f0, CKDIS, 0x0000); - + /* 0x9a DDRCSR Take subsystem out of idle */ data16 = pci_read_config16(ctrl->f0, DDRCSR); data16 &= ~(7 << 12); data16 |= (3 << 12); /* use dual channel lock step */ pci_write_config16(ctrl->f0, DDRCSR, data16); - + /* program row size DRB */ spd_set_ram_size(ctrl, mask); /* program page size DRA */ spd_set_row_attributes(ctrl, mask); - /* program DRT timing values */ + /* program DRT timing values */ cas_latency = spd_set_drt_attributes(ctrl, mask, drc); for(i=0;i<8;i++) { /* loop throught each dimm to test for row */ @@ -1097,7 +1097,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("\n"); /* Apply NOP */ do_delay(); - + write32(BAR + 0x100, (0x03000000 | (i<<20))); write32(BAR+0x100, (0x83000000 | (i<<20))); @@ -1107,12 +1107,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 = read32(BAR+DCALCSR); } - + /* Apply NOP */ do_delay(); - for(cs=0;cs<8;cs++) { - write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); + for(cs=0;cs<8;cs++) { + write32(BAR + DCALCSR, (0x83000000 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); @@ -1120,7 +1120,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharg all banks */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1130,10 +1130,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* EMRS dll's enabled */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ /* fixme hard code AL additive latency */ write32(BAR+DCALADDR, 0x0b940001); @@ -1158,7 +1158,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) else /* CAS Latency 2.5 */ mode_reg = 0x016a0000; } - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, mode_reg); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1170,7 +1170,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) do_delay(); do_delay(); do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { if ((drc & 3) == 2) /* DDR2 */ write32(BAR+DCALADDR, 0x04000000); else /* DDR1 */ @@ -1180,17 +1180,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Do 2 refreshes */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); data32 = read32(BAR+DCALCSR); while(data32 & 0x80000000) @@ -1198,33 +1198,33 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } do_delay(); /* for good luck do 6 more */ - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x83000001 | (cs<<20))); } do_delay(); /* MRS reset dll's normal */ do_delay(); - for(cs=0;cs<8;cs++) { + for(cs=0;cs<8;cs++) { write32(BAR+DCALADDR, (mode_reg & ~(1<<24))); write32(BAR+DCALCSR, (0x83000003 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1249,7 +1249,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) write32(BAR+DCALCSR, 0x0000000f); /* DDR1 This is test code to copy some codes in the factory setup */ - + write32(BAR, 0x00100000); if ((drc & 3) == 2) { /* DDR2 */ @@ -1259,9 +1259,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* receive enable calibration */ set_receive_enable(ctrl); - + /* DQS */ - pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); + pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) { write32(cnt, dqs_data[i]); } @@ -1270,7 +1270,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Enable refresh */ /* 0x7c DRC */ data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ @@ -1278,7 +1278,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) for(i=0;i<64;i+=4) { write32(BAR+DCALDATA+i, 0x00000000); } - + for(cs=0;cs<8;cs++) { write32(BAR+DCALCSR, (0x830831d8 | (cs<<20))); data32 = read32(BAR+DCALCSR); @@ -1298,22 +1298,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) break; } print_debug("Done\n"); - + /* Set initialization complete */ /* 0x7c DRC */ drc |= (1 << 29); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); /* Set the ecc mode */ - pci_write_config32(ctrl->f0, DRC, drc); + pci_write_config32(ctrl->f0, DRC, drc); /* Enable memory scrubbing */ - /* 0x52 MCHSCRB */ + /* 0x52 MCHSCRB */ data16 = pci_read_config16(ctrl->f0, MCHSCRB); data16 &= ~0x0f; data16 |= ((2 << 2) | (2 << 0)); - pci_write_config16(ctrl->f0, MCHSCRB, data16); + pci_write_config16(ctrl->f0, MCHSCRB, data16); /* The memory is now setup, use it */ cache_lbmem(MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index d6400d5859..42f624aaf7 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -59,7 +59,7 @@ static void pcie_bus_enable_resources(struct device *dev) if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n"); pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8); - + dev->command |= PCI_COMMAND_IO; dev->command |= PCI_COMMAND_MEMORY; } diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 5a4a328e44..7aeef29c84 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -34,7 +34,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000, PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a, - PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0, + PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0, }; int i; int max; @@ -89,7 +89,7 @@ static struct dimm_size spd_get_dimm_size(u16 device) if (value < 0) goto hw_err; value &= 0xff; value <<= 8; - + low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); if (low < 0) goto hw_err; value = value | (low & 0xff); @@ -143,7 +143,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask) { int i; int cum; - + for (i = cum = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; if (dimm_mask & (1 << i)) { @@ -212,7 +212,7 @@ static u8 spd_detect_dimms(const struct mem_controller *ctrl) } -static int spd_set_row_attributes(const struct mem_controller *ctrl, +static int spd_set_row_attributes(const struct mem_controller *ctrl, u8 dimm_mask) { int value; @@ -258,7 +258,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, /* set device width (x8) */ dra |= (1 << 4); dra |= (1 << 10); - + /* set device type (registered) */ dra |= (1 << 14); @@ -278,7 +278,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, } -static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, +static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, u8 dimm_mask, u32 drc) { int i; @@ -409,7 +409,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, return val; } -static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, +static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, u8 dimm_mask) { int value; @@ -486,7 +486,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, return drc; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { u8 dimm_mask; int i; @@ -506,7 +506,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) u32 dimm,i; u32 data32; u32 t4; - + /* Set up northbridge values */ /* ODT enable */ pci_write_config32(ctrl->f0, SDRC, 0xa0002c30); @@ -581,17 +581,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) data32 = data32 | (3 << 5); /* temp turn off ODT */ /* Set DRAM controller mode */ pci_write_config32(ctrl->f0, DRC, data32); - + /* Turn the clocks on */ pci_write_config16(ctrl->f0, CKDIS, 0x0000); - + /* Program row size */ spd_set_ram_size(ctrl, mask); - + /* Program row attributes */ spd_set_row_attributes(ctrl, mask); - /* Program timing values */ + /* Program timing values */ mode_reg = spd_set_drt_attributes(ctrl, mask, drc); dump_dcal_regs(); @@ -608,14 +608,14 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Apply NOP */ udelay(16); for (cs = 0; cs < 2; cs++) { print_debug("NOP CS"); print_debug_hex8(cs); print_debug("\n"); - write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); + write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); data32 = read32(BAR+DCALCSR); while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); @@ -623,7 +623,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharge all banks */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("Precharge CS"); print_debug_hex8(cs); print_debug("\n"); @@ -633,10 +633,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* EMRS: Enable DLLs, set OCD calibration mode to default */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("EMRS CS"); print_debug_hex8(cs); print_debug("\n"); @@ -648,7 +648,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* MRS: Reset DLLs */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("MRS CS"); print_debug_hex8(cs); print_debug("\n"); @@ -661,7 +661,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Precharge all banks */ udelay(48); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("Precharge CS"); print_debug_hex8(cs); print_debug("\n"); @@ -671,11 +671,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + /* Do 2 refreshes */ for (i = 0; i < 2; i++) { udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("Refresh CS"); print_debug_hex8(cs); print_debug("\n"); @@ -688,7 +688,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* MRS: Set DLLs to normal */ udelay(16); - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { print_debug("MRS CS"); print_debug_hex8(cs); print_debug("\n"); @@ -734,7 +734,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) while (data32 & 0x80000000) data32 = read32(BAR+DCALCSR); } - + dump_dcal_regs(); /* Adjust RCOMP */ @@ -746,11 +746,11 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) dump_dcal_regs(); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); write32(BAR+DCALCSR, 0x0008000f); /* Clear memory and init ECC */ - for (cs = 0; cs < 2; cs++) { + for (cs = 0; cs < 2; cs++) { if (!(mask & (1<<cs))) continue; print_debug("clear memory CS"); @@ -779,10 +779,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) drc |= (1 << 29); drc |= (3 << 30); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(ctrl->f0, DRC, data32); /* Set the ECC mode */ - pci_write_config32(ctrl->f0, DRC, drc); + pci_write_config32(ctrl->f0, DRC, drc); /* The memory is now set up--use it */ cache_lbmem(MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 4de84d3472..99f043f778 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -30,7 +30,7 @@ config SDRAMPWR_4DIMM This option affects how the SDRAMC register is programmed. Memory clock signals will not be routed properly if this option is set wrong. - + If your board has 4 DIMM slots, you must use select this option, in your Kconfig file of the board. On boards with 3 DIMM slots, do _not_ select this option. diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index b437755213..34f4fd4fed 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -8,8 +8,8 @@ static void dump_spd_registers(void) device = DIMM_SPD_BASE + i; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 97311c5fdf..2edbe8ba3f 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -72,10 +72,10 @@ #define AGPCTRL 0xb0 /* AGP Control Register (0x00000000) */ #define APSIZE 0xb4 /* Aperture Size Control Register (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table (0x00000000) */ - + #define MBFS 0xca /* Memory Buffer Frequency Select (0x000000). */ #define BSPAD 0xd0 /* BIOS Scratch Pad (0x000..000). */ -#define BSPAD0 0xd0 /* These are free for our use. */ +#define BSPAD0 0xd0 /* These are free for our use. */ #define BSPAD1 0xd1 #define BSPAD2 0xd2 #define BSPAD3 0xd3 diff --git a/src/northbridge/intel/i440lx/Makefile.inc b/src/northbridge/intel/i440lx/Makefile.inc index f4ef7d49c2..c6b480940f 100644 --- a/src/northbridge/intel/i440lx/Makefile.inc +++ b/src/northbridge/intel/i440lx/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.o +driver-y += northbridge.o diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index ebe38afd51..7ebc002c72 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -33,7 +33,7 @@ #include "northbridge.h" #include "i440lx.h" -/* This code is mostly same as 440BX created by Uwe Hermann, +/* This code is mostly same as 440BX created by Uwe Hermann, * i done only very minor changes like renamed functions to 440lx etc * Maciej */ diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c index 61ddde98ca..d8cebb2808 100644 --- a/src/northbridge/intel/i440lx/raminit.c +++ b/src/northbridge/intel/i440lx/raminit.c @@ -61,14 +61,14 @@ static const long register_values[] = { // 0x04 == bit 10 // BASE is 0x8A but we dont want bit 9 or 10 have ENABLED so 0x8C PACCFG + 1, 0x38, 0x8c, - + DBC, 0x00, 0xC3, DRT, 0x00, 0xFF, DRT+1, 0x00, 0xFF, DRAMC, 0x00, 0x00, /* disable refresh for now. */ - DRAMT, 0x00, 0x00, + DRAMT, 0x00, 0x00, PAM0, 0x00, 0x30, // everything is a mem PAM1, 0x00, 0x33, @@ -109,7 +109,7 @@ static void do_ram_command(u32 command) u32 addr, addr_offset; /* Configure the RAM command. */ - reg16 = pci_read_config16(NB, DRAMXC); + reg16 = pci_read_config16(NB, DRAMXC); reg16 &= 0xff1f; /* Clear bits 7-5. */ reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */ pci_write_config16(NB, DRAMXC, reg16); @@ -127,7 +127,7 @@ static void do_ram_command(u32 command) addr_offset = 0; caslatency = 3; /* TODO: Dynamically get CAS latency later. */ - /* before translation it is + /* before translation it is * * M[02:00] Burst Length * M[03:03] Burst Type @@ -153,7 +153,7 @@ static void do_ram_command(u32 command) * must be left shifted by 3 * so possible formula is (caslatency <<4)|(burst_type << 1)|(burst length) * then << 3 shift to compensate shift in Memory Controller - */ + */ if (command == RAM_COMMAND_MRS) { if (caslatency == 3) addr_offset = 0x1d0; @@ -194,7 +194,7 @@ static void spd_enable_refresh(void) /* this chipset offer only two choices regarding refresh * refresh disabled, or refresh normal */ - + pci_write_config8(NB, DRAMC, reg | 0x01); reg = pci_read_config8(NB, DRAMC); @@ -216,10 +216,10 @@ static void northbridge_init(void) pci_write_config32(NB, APBASE, reg32); #ifdef DEBUG_RAM_SETUP - /* - * apbase dont get set still, no idea what i have doing wrong yet, + /* + * apbase dont get set still, no idea what i have doing wrong yet, * i am almost sure that somehow i set it by mistake once, but can't - * repeat that. + * repeat that. */ reg32 = pci_read_config32(NB, APBASE); PRINT_DEBUG("APBASE "); @@ -238,11 +238,11 @@ static void sdram_set_registers(void) int i, max; /* nice banner with FSB shown? do we have - * any standart policy about such things? + * any standart policy about such things? */ #if 0 uint16_t reg16; - reg16 = pci_read_config16(NB, PACCFG); + reg16 = pci_read_config16(NB, PACCFG); printk(BIOS_DEBUG, "i82443LX Host Freq: 6%C MHz\n", (reg16 & 0x4000) ? '0' : '6'); #endif @@ -261,8 +261,8 @@ static void sdram_set_registers(void) reg |= register_values[i + 2] & ~(register_values[i + 1]); pci_write_config8(NB, register_values[i], reg); - /* - * i am not sure if that is needed, but was usefull + /* + * i am not sure if that is needed, but was usefull * for me to confirm what got written */ #ifdef DEBUG_RAM_SETUP @@ -282,7 +282,7 @@ static void sdram_set_registers(void) #endif } - PRINT_DEBUG("Northbridge atexit sdram set registers\n"); + PRINT_DEBUG("Northbridge atexit sdram set registers\n"); DUMPNORTH(); } @@ -293,9 +293,9 @@ static void sdram_set_spd_registers(void) u16 memsize = 0; for (i = 0; i < DIMM_SOCKETS; i++) { - uint16_t ds = 0; // dimm size + uint16_t ds = 0; // dimm size int j; - /* this code skips second bank on each socket (no idea how to fix it now) + /* this code skips second bank on each socket (no idea how to fix it now) */ PRINT_DEBUG("DIMM"); @@ -321,8 +321,8 @@ static void sdram_set_spd_registers(void) /* This is more or less crude hack - * allowing to run this target under qemu (even if that is not really - * same hardware emulated), + * allowing to run this target under qemu (even if that is not really + * same hardware emulated), * probably some kconfig expert option should be added to enable/disable * this nicelly */ @@ -333,10 +333,10 @@ static void sdram_set_spd_registers(void) // todo: support for bank with not equal sizes as per jedec standart? - + /* * because density is reported in units of 4Mbyte - * and rows in device are just value, + * and rows in device are just value, * and for setting registers we need value in 8Mbyte units */ @@ -348,7 +348,7 @@ static void sdram_set_spd_registers(void) pci_write_config8(NB, DRB + (2*i), memsize); pci_write_config8(NB, DRB + (2*i) + 1, memsize); if (ds > 0) { - /* i have no idea why pci_read_config16 not work for + /* i have no idea why pci_read_config16 not work for * me correctly here */ ds = pci_read_config8(NB, DRT+1); @@ -364,9 +364,9 @@ static void sdram_set_spd_registers(void) PRINT_DEBUG_HEX16(ds); PRINT_DEBUG("\n"); - /* + /* * modify DRT register if current row isn't empty - * code assume its SDRAM plugged (should check if its sdram or EDO, + * code assume its SDRAM plugged (should check if its sdram or EDO, * edo would have 0x00 as constand instead 0x10 for SDRAM * also this code is buggy because ignores second row of each dimm socket */ @@ -400,7 +400,7 @@ static void sdram_set_spd_registers(void) pci_write_config8(NB, DRAMC, 0x00); /* Cas latency 3, and other shouldbe properly from spd too */ - pci_write_config8(NB, DRAMT, 0xAC); + pci_write_config8(NB, DRAMT, 0xAC); /* TODO? */ pci_write_config8(NB, PCI_LATENCY_TIMER, 0x40); diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c index 87b039f5f5..5bddbb60a3 100644 --- a/src/northbridge/intel/i82810/debug.c +++ b/src/northbridge/intel/i82810/debug.c @@ -8,8 +8,8 @@ static void dump_spd_registers(void) device = DIMM_SPD_BASE + i; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c index fbb64f6088..81148e313d 100644 --- a/src/northbridge/intel/i82810/raminit.c +++ b/src/northbridge/intel/i82810/raminit.c @@ -312,7 +312,7 @@ static void set_dram_buffer_strength(void) SPD_NUM_DIMM_BANKS) > 1; d1.ss = !d1.ds; } - + buff_sc = 0; /* Tame the beast... */ @@ -350,7 +350,7 @@ static void set_dram_buffer_strength(void) buff_sc |= 1 << 14; if (!d0.size && d1.size) buff_sc |= 1 << 15; - + print_debug("BUFF_SC calculated to 0x"); print_debug_hex16(buff_sc); print_debug("\n"); @@ -371,7 +371,7 @@ static void sdram_set_registers(void) /* Ideally, this should be R/W for as many ranges as possible. */ pci_write_config8(PCI_DEV(0, 0, 0), PAMR, 0xff); - + /* Set size for onboard-VGA framebuffer. */ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM); reg8 &= 0x3f; /* Disable graphics (for now). */ diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h index 5a06dd171d..8c558a5699 100644 --- a/src/northbridge/intel/i82810/raminit.h +++ b/src/northbridge/intel/i82810/raminit.h @@ -27,7 +27,7 @@ /* DIMM0 is at 0x50, DIMM1 is at 0x51. */ #define DIMM_SPD_BASE 0x50 -/* The following table has been bumped over to this header to avoid clutter in +/* The following table has been bumped over to this header to avoid clutter in * raminit.c. It's used to translate the value read from SPD Byte 31 to a value * the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most * northbridges have some sort of simple calculation that can be done for this, @@ -38,7 +38,7 @@ /* TODO: Find a better way of doing this. */ static const uint8_t translate_spd_to_i82810[] = { - /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB + /* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB * side can't be either, at least for now. */ /* TODO: For above case, only use the other side if > 4MB, and get some diff --git a/src/northbridge/intel/i82830/i82830_smihandler.c b/src/northbridge/intel/i82830/i82830_smihandler.c index 515be54acc..c9c7bcb27f 100644 --- a/src/northbridge/intel/i82830/i82830_smihandler.c +++ b/src/northbridge/intel/i82830/i82830_smihandler.c @@ -194,10 +194,10 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i+=16; continue; } - + mbi_header = (mbi_header_t *)&mbi[i]; len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + mbi_header->name_len, 16); - + if (obj_header->objnum == count) { #ifdef DEBUG_SMI_I82830 if (mbi_header->name_len == 0xff) { @@ -224,7 +224,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i += len; count++; } - if (obj_header->banner.retsts == MSH_IF_NOT_FOUND) + if (obj_header->banner.retsts == MSH_IF_NOT_FOUND) printk(BIOS_DEBUG, "| |- MBI object #%d not found.\n", obj_header->objnum); break; } @@ -251,10 +251,10 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i+=16; continue; } - + mbi_header = (mbi_header_t *)&mbi[i]; len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + mbi_header->name_len, 16); - + if (getobj->objnum == count) { printk(BIOS_DEBUG, "| |- len = %x\n", len); memcpy((void *)(getobj->buffer + OBJ_OFFSET), @@ -270,7 +270,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id) i += len; count++; } - if (getobj->banner.retsts == MSH_IF_NOT_FOUND) + if (getobj->banner.retsts == MSH_IF_NOT_FOUND) printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum); break; } diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c index 66b591b548..21c677960e 100644 --- a/src/northbridge/intel/i82830/vga.c +++ b/src/northbridge/intel/i82830/vga.c @@ -68,7 +68,7 @@ static void vga_init(device_t dev) #define PIPE_A_TV (1 << 3) #define PIPE_B_CRT (1 << 8) #define PIPE_B_TV (1 << 10) - printk(BIOS_DEBUG, "Enabling TV-Out\n"); + printk(BIOS_DEBUG, "Enabling TV-Out\n"); void runInt10(void); M.x86.R_AX = 0x5f64; M.x86.R_BX = 0x0001; // Set Display Device, force execution diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c index c353776c12..2f7d5342a1 100644 --- a/src/northbridge/intel/i855/debug.c +++ b/src/northbridge/intel/i855/debug.c @@ -31,8 +31,8 @@ static void print_debug_pci_dev(unsigned dev) static inline void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -51,7 +51,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -70,8 +70,8 @@ static void dump_pci_device(unsigned dev) static inline void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -93,8 +93,8 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -130,7 +130,7 @@ static inline void dump_smbus_registers(void) print_debug("smbus: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { - int status; + int status; unsigned char byte; if ((j & 0xf) == 0) { print_debug("\n"); @@ -147,5 +147,5 @@ static inline void dump_smbus_registers(void) print_debug_char(' '); } print_debug("\n"); - } + } } diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 03bf3a93b6..3495fb6cfb 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -79,15 +79,15 @@ static void pci_domain_set_resources(device_t dev) { device_t mc_dev; uint32_t pci_tolm; - + printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device); - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev->link[0].children->sibling; printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor); printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device); - + if (mc_dev) { /* Figure out which areas are/should be occupied by RAM. * This is all computed in kilobytes and converted to/from @@ -117,7 +117,7 @@ static void pci_domain_set_resources(device_t dev) /* Write the ram configuration registers, * preserving the reserved bits. */ - + /* Report the memory regions */ printk(BIOS_DEBUG, "tomk = %ld\n", tomk); printk(BIOS_DEBUG, "tolmk = %ld\n", tolmk); @@ -143,7 +143,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -}; +}; static void cpu_bus_init(device_t dev) { diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 5d71a27ca1..386eda10bb 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -17,7 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - + #include <sdram_mode.h> #include <delay.h> @@ -28,7 +28,7 @@ * Set only what I need until it works, then make it figure things out on boot * assumes only one dimm is populated */ - + static void sdram_set_registers(const struct mem_controller *ctrl) { /* @@ -40,7 +40,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) static void spd_set_row_attributes(const struct mem_controller *ctrl) { uint16_t dra_reg; - + dra_reg = 0x7733; pci_write_config16(ctrl->d0, 0x50, dra_reg); } @@ -48,7 +48,7 @@ static void spd_set_row_attributes(const struct mem_controller *ctrl) static void spd_set_dram_controller_mode(const struct mem_controller *ctrl) { uint32_t drc_reg; - + /* drc_reg = 0x00009101; */ drc_reg = 0x00009901; pci_write_config32(ctrl->d0, 0x70, drc_reg); @@ -57,7 +57,7 @@ static void spd_set_dram_controller_mode(const struct mem_controller *ctrl) static void spd_set_dram_timing(const struct mem_controller *ctrl) { uint32_t drt_reg; - + drt_reg = 0x2a004405; pci_write_config32(ctrl->d0, 0x60, drt_reg); } @@ -73,7 +73,7 @@ static void spd_set_dram_size(const struct mem_controller *ctrl) static void spd_set_dram_pwr_management(const struct mem_controller *ctrl) { uint32_t pwrmg_reg; - + pwrmg_reg = 0x10f10430; pci_write_config32(ctrl->d0, 0x68, pwrmg_reg); } @@ -97,31 +97,31 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl) pci_write_config32(PCI_DEV(0, 0, 0), 0x2c, 0x35808086); pci_write_config32(PCI_DEV(0, 0, 0), 0x48, 0xfec10000); pci_write_config32(PCI_DEV(0, 0, 0), 0x50, 0x00440100); - + pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x11111000); - + pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0002); */ pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0044); /* pci_write_config16(PCI_DEV(0, 0, 0), 0x52, 0x0000); */ - pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x33333000); + pci_write_config32(PCI_DEV(0, 0, 0), 0x58, 0x33333000); pci_write_config32(PCI_DEV(0, 0, 0), 0x5c, 0x33333333); /* pci_write_config32(PCI_DEV(0, 0, 0), 0x60, 0x0000390a); pci_write_config32(PCI_DEV(0, 0, 0), 0x74, 0x02006056); pci_write_config32(PCI_DEV(0, 0, 0), 0x78, 0x00800001); */ - pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x00000001); - + pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, 0x00000001); + pci_write_config32(PCI_DEV(0, 0, 0), 0xbc, 0x00001020); /* pci_write_config32(PCI_DEV(0, 0, 0), 0xfc, 0x00000109); */ /* 0:0.1 */ - pci_write_config32(ctrl->d0, 0x74, 0x00000001); + pci_write_config32(ctrl->d0, 0x74, 0x00000001); pci_write_config32(ctrl->d0, 0x78, 0x001fe974); pci_write_config32(ctrl->d0, 0x80, 0x00af0039); pci_write_config32(ctrl->d0, 0x84, 0x0000033c); @@ -133,7 +133,7 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl) pci_write_config32(ctrl->d0, 0xb8, 0x000055d4); pci_write_config32(ctrl->d0, 0xbc, 0x024acd38); pci_write_config32(ctrl->d0, 0xc0, 0x00000003); - + /* 0:0.3 */ /* pci_write_config32(PCI_DEV(0, 0, 3), 0x2c, 0x35858086); @@ -147,12 +147,12 @@ static void spd_set_undocumented_registers(const struct mem_controller *ctrl) pci_write_config32(PCI_DEV(0, 0, 3), 0x7c, 0x0284007f); pci_write_config32(PCI_DEV(0, 0, 3), 0x84, 0x000000ef); */ - + /* pci_write_config16(PCI_DEV(0, 0, 3), 0xc0, 0x0200); pci_write_config16(PCI_DEV(0, 0, 3), 0xc0, 0x0400); */ - + /* pci_write_config32(PCI_DEV(0, 0, 3), 0xc4, 0x00000000); pci_write_config32(PCI_DEV(0, 0, 3), 0xd8, 0xff00c308); @@ -180,7 +180,7 @@ static void ram_command(const struct mem_controller *ctrl, uint32_t addr) { uint32_t drc_reg; - + drc_reg = pci_read_config32(ctrl->d0, 0x70); drc_reg &= ~(7 << 4); drc_reg |= (command << 4); @@ -195,12 +195,12 @@ static void ram_command_mrs(const struct mem_controller *ctrl, { uint32_t drc_reg; uint32_t adjusted_mode; - + drc_reg = pci_read_config32(ctrl->d0, 0x70); drc_reg &= ~(7 << 4); drc_reg |= (command << 4); pci_write_config8(ctrl->d0, 0x70, drc_reg); - /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */ + /* Host address lines [13:3] map to DIMM address lines [11, 9:0] */ adjusted_mode = ((mode & 0x800) << (13 - 11)) | ((mode & 0x3ff) << (12 - 9)); print_debug("Setting mode: "); print_debug_hex32(adjusted_mode + addr); @@ -211,7 +211,7 @@ static void ram_command_mrs(const struct mem_controller *ctrl, static void set_initialize_complete(const struct mem_controller *ctrl) { uint32_t drc_reg; - + drc_reg = pci_read_config32(ctrl->d0, 0x70); drc_reg |= (1 << 29); pci_write_config32(ctrl->d0, 0x70, drc_reg); @@ -224,7 +224,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("Ram enable 1\n"); delay(); delay(); - + print_debug("Ram enable 2\n"); ram_command(ctrl, 1, 0); ram_command(ctrl, 1, rank1); @@ -242,17 +242,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, rank1); delay(); delay(); - + print_debug("Ram enable 5\n"); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, 0); ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, rank1); - + print_debug("Ram enable 6\n"); ram_command(ctrl, 2, 0); ram_command(ctrl, 2, rank1); delay(); delay(); - + print_debug("Ram enable 7\n"); for(i = 0; i < 8; i++) { ram_command(ctrl, 6, 0); @@ -270,19 +270,19 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) ram_command(ctrl, 7, rank1); delay(); delay(); - + print_debug("Ram enable 9\n"); set_initialize_complete(ctrl); - + delay(); delay(); delay(); - + print_debug("After configuration:\n"); /* dump_pci_devices(); */ - + /* - print_debug("\n\n***** RAM TEST *****\n"); + print_debug("\n\n***** RAM TEST *****\n"); ram_check(0, 0xa0000); ram_check(0x100000, 0x40000000); */ diff --git a/src/northbridge/intel/i855/reset_test.c b/src/northbridge/intel/i855/reset_test.c index b48b4a3764..40f2f89973 100644 --- a/src/northbridge/intel/i855/reset_test.c +++ b/src/northbridge/intel/i855/reset_test.c @@ -28,12 +28,12 @@ static int bios_reset_detected(void) { uint32_t dword; - + dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC); - + if( (dword & DRC_DONE) != 0 ) { return 1; - } - + } + return 0; } diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 6002a76876..dd095ca7b3 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -1,6 +1,6 @@ /* * This file is part of the coreboot project. - * + * * Copyright (C) 2007-2008 coresystems GmbH * * This program is free software; you can redistribute it and/or @@ -26,8 +26,8 @@ static inline void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -64,8 +64,8 @@ static inline void dump_pci_device(unsigned dev) static inline void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -86,7 +86,7 @@ static inline void dump_spd_registers(void) int status = 0; int i; printk(BIOS_DEBUG, "\ndimm %02x", device); - + for(i = 0; (i < 256) ; i++) { if ((i % 16) == 0) { printk(BIOS_DEBUG, "\n%02x: ", i); @@ -94,7 +94,7 @@ static inline void dump_spd_registers(void) status = smbus_read_byte(device, i); if (status < 0) { printk(BIOS_DEBUG, "bad device: %02x\n", -status); - break; + break; } printk(BIOS_DEBUG, "%02x ", status); } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index db24c93a0d..3c54b98855 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -199,7 +199,7 @@ static int sdram_capabilities_two_dimms_per_channel(void) return (reg8 != 0); } -// TODO check if we ever need this function +// TODO check if we ever need this function #if 0 static int sdram_capabilities_MEM4G_disable(void) { |