diff options
Diffstat (limited to 'src/northbridge/via/cn700/raminit.c')
| -rw-r--r-- | src/northbridge/via/cn700/raminit.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index bddb4448fe..72fb0c5a26 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -183,7 +183,7 @@ static void sdram_set_size(const struct mem_controller *ctrl) } if (result == 0xff) - die("DRAM module size too big, not supported by CN700\r\n"); + die("DRAM module size too big, not supported by CN700\n"); pci_write_config8(ctrl->d0f3, 0x40, result); pci_write_config8(ctrl->d0f3, 0x48, 0x00); @@ -389,30 +389,30 @@ static void sdram_enable(device_t dev, unsigned long rank_address) u8 i; /* 1. Apply NOP. */ - PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\r\n"); + PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n"); do_ram_command(dev, RAM_COMMAND_NOP); udelay(100); read32(rank_address + 0x10); /* 2. Precharge all. */ udelay(400); - PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n"); do_ram_command(dev, RAM_COMMAND_PRECHARGE); read32(rank_address + 0x10); /* 3. Mode register set. */ - PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); do_ram_command(dev, RAM_COMMAND_MRS); read32(rank_address + 0x120000); /* EMRS DLL Enable */ read32(rank_address + 0x800); /* MRS DLL Reset */ /* 4. Precharge all again. */ - PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n"); + PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n"); do_ram_command(dev, RAM_COMMAND_PRECHARGE); read32(rank_address + 0x0); /* 5. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n"); + PRINT_DEBUG_MEM("RAM Enable 3: CBR\n"); do_ram_command(dev, RAM_COMMAND_CBR); for (i = 0; i < 8; i++) { read32(rank_address + 0x20); @@ -420,7 +420,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address) } /* 6. Mode register set. */ - PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n"); + PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); /* Safe value for now, BL=8, WR=5, CAS=4 */ /* * (E)MRS values are from the BPG. No direct explanation is given, but @@ -433,7 +433,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address) read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */ /* 8. Normal operation */ - PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n"); + PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n"); do_ram_command(dev, RAM_COMMAND_NORMAL); read32(rank_address + 0x30); } |