diff options
Diffstat (limited to 'src/northbridge/via/vx900')
| -rw-r--r-- | src/northbridge/via/vx900/lpc.c | 6 | ||||
| -rw-r--r-- | src/northbridge/via/vx900/traf_ctrl.c | 12 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 3cff6b0bf6..61a8a7b96a 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -139,10 +139,10 @@ static void vx900_lpc_ioapic_setup(device_t dev) /* The base address of this IOAPIC _must_ be at 0xfec00000. * Don't move this value to a #define, as people might think it's * configurable. It is not. */ - const u32 base = config->base; - if (base != 0xfec00000) { + const void *base = config->base; + if (base != (void *)0xfec00000) { printk(BIOS_ERR, "ERROR: South module IOAPIC base should be at " - "0xfec00000\n but we found it at 0x%.8x\n", base); + "0xfec00000\n but we found it at %p\n", base); return; } diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c index 5183391c76..fb151935b2 100644 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -80,24 +80,24 @@ static void vx900_north_ioapic_setup(device_t dev) * be between 0xfec00000 and 0xfecfff00 * be 256-byte aligned */ - if ((config->base < 0xfec0000 || config->base > 0xfecfff00) - || ((config->base & 0xff) != 0)) { + if ((config->base < (void *)0xfec0000 || config->base > (void *)0xfecfff00) + || (((uintptr_t)config->base & 0xff) != 0)) { printk(BIOS_ERR, "ERROR: North module IOAPIC base should be " "between 0xfec00000 and 0xfecfff00\n" "and must be aligned to a 256-byte boundary, " - "but we found it at 0x%.8x\n", config->base); + "but we found it at 0x%p\n", config->base); return; } printk(BIOS_DEBUG, "VX900 TRAF_CTR: Setting up the north module IOAPIC " - "at 0%.8x\n", config->base); + "at %p\n", config->base); /* First register of the IOAPIC base */ - base_val = (config->base >> 8) & 0xff; + base_val = (((uintptr_t)config->base) >> 8) & 0xff; pci_write_config8(dev, 0x41, base_val); /* Second register of the base. * Bit[7] also enables the IOAPIC and bit[5] enables MSI cycles */ - base_val = (config->base >> 16) & 0xf; + base_val = (((uintptr_t)config->base) >> 16) & 0xf; pci_mod_config8(dev, 0x40, 0, base_val | (1 << 7) | (1 << 5)); } |