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-rw-r--r--src/northbridge/via/vx800/timing_setting.c19
-rw-r--r--src/northbridge/via/vx900/raminit_ddr3.c22
2 files changed, 19 insertions, 22 deletions
diff --git a/src/northbridge/via/vx800/timing_setting.c b/src/northbridge/via/vx800/timing_setting.c
index df903049b9..3bd45e40ae 100644
--- a/src/northbridge/via/vx800/timing_setting.c
+++ b/src/northbridge/via/vx800/timing_setting.c
@@ -117,8 +117,7 @@ void SetTrp(DRAM_SYS_ATTR * DramAttr)
/*Calculate clock,this value should be 2T,3T,4T,5T */
}
Tmp =
- (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) -
- 1) / ((DramAttr->DramCyc) << 2));
+ (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2);
PRINT_DEBUG_MEM("Trp = ");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -168,8 +167,7 @@ void SetTrcd(DRAM_SYS_ATTR * DramAttr)
}
/*Calculate clock,this value should be 2T,3T,4T,5T */
Tmp =
- (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) -
- 1) / ((DramAttr->DramCyc) << 2));
+ (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2);
PRINT_DEBUG_MEM("Trcd =");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -213,7 +211,7 @@ void SetTras(DRAM_SYS_ATTR * DramAttr)
}
/*Calculate clock,value range 5T-20T */
- Tmp = (u16) ((Max * 100 + DramAttr->DramCyc - 1) / (DramAttr->DramCyc));
+ Tmp = (u16) CEIL_DIV((Max * 100), DramAttr->DramCyc);
PRINT_DEBUG_MEM("Tras =");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -288,7 +286,7 @@ void SetTrfc(DRAM_SYS_ATTR * DramAttr)
}
/*Calculate clock,value range 8T-71T */
- Tmp = (u16) ((Max + DramAttr->DramCyc - 1) / (DramAttr->DramCyc));
+ Tmp = (u16) CEIL_DIV(Max, DramAttr->DramCyc);
PRINT_DEBUG_MEM("Trfc = ");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -334,8 +332,7 @@ void SetTrrd(DRAM_SYS_ATTR * DramAttr)
/*Calculate clock,this value should be 2T,3T,4T,5T */
Tmp =
- (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) -
- 1) / ((DramAttr->DramCyc) << 2));
+ (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2);
PRINT_DEBUG_MEM("Trrd =");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -378,7 +375,7 @@ void SetTwr(DRAM_SYS_ATTR * DramAttr)
}
}
/*Calculate clock */
- Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T,3T,4T,5T
+ Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T,3T,4T,5T
PRINT_DEBUG_MEM("Twr = ");
PRINT_DEBUG_MEM_HEX16(Tmp);
PRINT_DEBUG_MEM("\r");
@@ -421,7 +418,7 @@ void SetTwtr(DRAM_SYS_ATTR * DramAttr)
}
}
/*Calculate clock */
- Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T
+ Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T
PRINT_DEBUG_MEM("Twtr =");
PRINT_DEBUG_MEM_HEX16(Tmp);
@@ -463,7 +460,7 @@ void SetTrtp(DRAM_SYS_ATTR * DramAttr)
}
}
/*Calculate clock */
- Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T
+ Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T
PRINT_DEBUG_MEM("Trtp =");
PRINT_DEBUG_MEM_HEX16(Tmp);
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index a69d6999c8..3979466bf0 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -575,7 +575,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
printram("Selected DRAM frequency: %u MHz\n", val32);
/* Find CAS and CWL latencies */
- val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tAA, ctrl->tCK);
printram("Minimum CAS latency : %uT\n", val);
/* Find lowest supported CAS latency that satisfies the minimum value */
while (!((ctrl->cas_supported >> (val - 4)) & 1)
@@ -594,30 +594,30 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc0, reg8);
/* Find tRCD */
- val = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRCD, ctrl->tCK);
printram("Selected tRCD : %uT\n", val);
reg8 = ((val - 4) & 0x7) << 4;
/* Find tRP */
- val = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRP, ctrl->tCK);
printram("Selected tRP : %uT\n", val);
reg8 |= ((val - 4) & 0x7);
pci_write_config8(MCU, 0xc1, reg8);
/* Find tRAS */
- val = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRAS, ctrl->tCK);
printram("Selected tRAS : %uT\n", val);
reg8 = ((val - 15) & 0x7) << 4;
/* Find tWR */
- ctrl->WR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK;
+ ctrl->WR = CEIL_DIV(ctrl->tWR, ctrl->tCK);
printram("Selected tWR : %uT\n", ctrl->WR);
reg8 |= ((ctrl->WR - 4) & 0x7);
pci_write_config8(MCU, 0xc2, reg8);
/* Find tFAW */
- tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK;
+ tFAW = CEIL_DIV(ctrl->tFAW, ctrl->tCK);
printram("Selected tFAW : %uT\n", tFAW);
/* Find tRRD */
- tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK;
+ tRRD = CEIL_DIV(ctrl->tRRD, ctrl->tCK);
printram("Selected tRRD : %uT\n", tRRD);
val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */
reg8 = ((val - 0) & 0x7) << 4;
@@ -625,11 +625,11 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc3, reg8);
/* Find tRTP */
- val = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRTP, ctrl->tCK);
printram("Selected tRTP : %uT\n", val);
reg8 = ((val & 0x3) << 4);
/* Find tWTR */
- val = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tWTR, ctrl->tCK);
printram("Selected tWTR : %uT\n", val);
reg8 |= ((val - 2) & 0x7);
pci_mod_config8(MCU, 0xc4, 0x3f, reg8);
@@ -642,7 +642,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
* Since we previously set RxC4[7]
*/
reg8 = pci_read_config8(MCU, 0xc5);
- val = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRFC, ctrl->tCK);
printram("Minimum tRFC : %uT\n", val);
if (val < 30) {
val = 0;
@@ -655,7 +655,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
pci_write_config8(MCU, 0xc5, reg8);
/* Where does this go??? */
- val = (ctrl->tRC + ctrl->tCK - 1) / ctrl->tCK;
+ val = CEIL_DIV(ctrl->tRC, ctrl->tCK);
printram("Required tRC : %uT\n", val);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 22:18:18 +0000