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-rw-r--r--src/northbridge/via/cn400/raminit.c52
-rw-r--r--src/northbridge/via/cn700/raminit.c16
-rw-r--r--src/northbridge/via/cx700/cx700_early_smbus.c20
-rw-r--r--src/northbridge/via/vt8601/raminit.c30
-rw-r--r--src/northbridge/via/vt8623/raminit.c52
-rw-r--r--src/northbridge/via/vx800/examples/romstage.c38
-rw-r--r--src/northbridge/via/vx800/vga.c2
-rw-r--r--src/northbridge/via/vx800/vx800_early_smbus.c30
8 files changed, 120 insertions, 120 deletions
diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c
index 577d53b05b..7f7c997077 100644
--- a/src/northbridge/via/cn400/raminit.c
+++ b/src/northbridge/via/cn400/raminit.c
@@ -151,7 +151,7 @@ static void ddr_ram_setup(void)
unsigned long bank_address;
- print_debug("CN400 RAM init starting\r\n");
+ print_debug("CN400 RAM init starting\n");
pci_write_config8(ctrl.d0f7, 0x75, 0x08);
@@ -176,7 +176,7 @@ static void ddr_ram_setup(void)
*/
c = 0;
b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM);
- //print_val("Detecting Memory\r\nNumber of Banks ",b);
+ //print_val("Detecting Memory\nNumber of Banks ",b);
// Only supporting 4 bank chips just now
if( b == 4 ){
@@ -186,7 +186,7 @@ static void ddr_ram_setup(void)
c = 0x01;
bank = 0x40;
b = smbus_read_byte(0x50, SPD_NUM_ROWS);
- //print_val("\r\nNumber of Rows ", b);
+ //print_val("\nNumber of Rows ", b);
if( b >= 0x0d ){ // 256/512Mb
@@ -199,7 +199,7 @@ static void ddr_ram_setup(void)
Read SPD byte 13, Primary DRAM width.
*/
b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH);
- //print_val("\r\nPrimary DRAM width", b);
+ //print_val("\nPrimary DRAM width", b);
if( b != 4 ) // not 64/128Mb (x4)
c = 0x81; // 256Mb
}
@@ -208,12 +208,12 @@ static void ddr_ram_setup(void)
Read SPD byte 4, Number of column addresses.
*/
b = smbus_read_byte(0x50, SPD_NUM_COLUMNS);
- //print_val("\r\nNo Columns ",b);
+ //print_val("\nNo Columns ",b);
if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr
if( b == 9 ) c |= 0x40; // 9 bit col addr
if( b == 8 ) c |= 0x20; // 8 bit col addr
- //print_val("\r\nMA type ", c);
+ //print_val("\nMA type ", c);
pci_write_config8(ctrl.d0f3, 0x50, c);
}
@@ -223,7 +223,7 @@ static void ddr_ram_setup(void)
/* else
{
- die("DRAM module size is not supported by CN400\r\n");
+ die("DRAM module size is not supported by CN400\n");
}
*/
@@ -281,7 +281,7 @@ static void ddr_ram_setup(void)
// SPD byte 5 # of physical banks
b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS);
- //print_val("\r\nNo Physical Banks ",b);
+ //print_val("\nNo Physical Banks ",b);
if( b == 2)
{
c <<=1;
@@ -289,7 +289,7 @@ static void ddr_ram_setup(void)
}
/* else
{
- die("Only a single DIMM is supported by EPIA-N(L)\r\n");
+ die("Only a single DIMM is supported by EPIA-N(L)\n");
}
*/
// set banks 1,2,3...
@@ -309,7 +309,7 @@ static void ddr_ram_setup(void)
/* Read SPD byte 18 CAS Latency */
b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES);
-/* print_debug("\r\nCAS Supported ");
+/* print_debug("\nCAS Supported ");
if(b & 0x04)
print_debug("2 ");
if(b & 0x08)
@@ -318,11 +318,11 @@ static void ddr_ram_setup(void)
print_debug("3");
c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
- print_val("\r\nCycle time at CL X (nS)", c);
+ print_val("\nCycle time at CL X (nS)", c);
c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND);
- print_val("\r\nCycle time at CL X-0.5 (nS)", c);
+ print_val("\nCycle time at CL X-0.5 (nS)", c);
c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD);
- print_val("\r\nCycle time at CL X-1 (nS)", c);
+ print_val("\nCycle time at CL X-1 (nS)", c);
*/
/* Scaling of Cycle Time SPD data */
/* 7 4 3 0 */
@@ -330,27 +330,27 @@ static void ddr_ram_setup(void)
bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if( b & 0x10 ){ // DDR offering optional CAS 3
- //print_debug("\r\nStarting at CAS 3");
+ //print_debug("\nStarting at CAS 3");
c = 0x30;
/* see if we can better it */
if( b & 0x08 ){ // DDR mandatory CAS 2.5
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
- //print_debug("\r\nWe can do CAS 2.5");
+ //print_debug("\nWe can do CAS 2.5");
c = 0x20;
}
}
if( b & 0x04 ){ // DDR mandatory CAS 2
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
- //print_debug("\r\nWe can do CAS 2");
+ //print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
}else{ // no optional CAS values just 2 & 2.5
- //print_debug("\r\nStarting at CAS 2.5");
+ //print_debug("\nStarting at CAS 2.5");
c = 0x20; // assume CAS 2.5
if( b & 0x04){ // Should always happen
if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
- //print_debug("\r\nWe can do CAS 2");
+ //print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
@@ -386,7 +386,7 @@ static void ddr_ram_setup(void)
b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME);
- //print_val("\r\ntRP ",b);
+ //print_val("\ntRP ",b);
if ( b >= (5 * bank)) {
c |= 0x03; // set tRP = 5T
}
@@ -404,7 +404,7 @@ static void ddr_ram_setup(void)
*/
b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY);
- //print_val("\r\ntRCD ",b);
+ //print_val("\ntRCD ",b);
if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T
else if ( b >= (4 * bank)) c |= 0x08; // set tRCD = 4T
@@ -421,8 +421,8 @@ static void ddr_ram_setup(void)
bank = bank >> 2;
b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
- //print_val("\r\ntRAS ",b);
- //print_val("\r\nBank ", bank);
+ //print_val("\ntRAS ",b);
+ //print_val("\nBank ", bank);
if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T
else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T
else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T
@@ -537,7 +537,7 @@ static void ddr_ram_setup(void)
c &= 0x08;
if ( c == 0x08 )
{
- print_debug("Setting Burst Length 8\r\n");
+ print_debug("Setting Burst Length 8\n");
/*
CPU Frequency Device 0 Function 2 Offset 54
@@ -723,7 +723,7 @@ static void ddr_ram_setup(void)
break;
}
- print_val("\r\nLow Bond ",i);
+ print_val("\nLow Bond ",i);
if( i < 0xff ){
c = i++;
for( ; i <0xff ; i++){
@@ -767,7 +767,7 @@ static void ddr_ram_setup(void)
print_val(" High Bond ",i);
c = ((i - c)<<1)/3 + c;
print_val(" Setting DQS delay",c);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config8(ctrl.d0f3,0x70,c);
}else{
pci_write_config8(ctrl.d0f3,0x70,0x67);
@@ -822,5 +822,5 @@ static void ddr_ram_setup(void)
/* VGA device. */
pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
- print_debug("CN400 raminit.c done\r\n");
+ print_debug("CN400 raminit.c done\n");
}
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index bddb4448fe..72fb0c5a26 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -183,7 +183,7 @@ static void sdram_set_size(const struct mem_controller *ctrl)
}
if (result == 0xff)
- die("DRAM module size too big, not supported by CN700\r\n");
+ die("DRAM module size too big, not supported by CN700\n");
pci_write_config8(ctrl->d0f3, 0x40, result);
pci_write_config8(ctrl->d0f3, 0x48, 0x00);
@@ -389,30 +389,30 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
u8 i;
/* 1. Apply NOP. */
- PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n");
do_ram_command(dev, RAM_COMMAND_NOP);
udelay(100);
read32(rank_address + 0x10);
/* 2. Precharge all. */
udelay(400);
- PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
do_ram_command(dev, RAM_COMMAND_PRECHARGE);
read32(rank_address + 0x10);
/* 3. Mode register set. */
- PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
do_ram_command(dev, RAM_COMMAND_MRS);
read32(rank_address + 0x120000); /* EMRS DLL Enable */
read32(rank_address + 0x800); /* MRS DLL Reset */
/* 4. Precharge all again. */
- PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
do_ram_command(dev, RAM_COMMAND_PRECHARGE);
read32(rank_address + 0x0);
/* 5. Perform 8 refresh cycles. Wait tRC each time. */
- PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 3: CBR\n");
do_ram_command(dev, RAM_COMMAND_CBR);
for (i = 0; i < 8; i++) {
read32(rank_address + 0x20);
@@ -420,7 +420,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
}
/* 6. Mode register set. */
- PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
/* Safe value for now, BL=8, WR=5, CAS=4 */
/*
* (E)MRS values are from the BPG. No direct explanation is given, but
@@ -433,7 +433,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
/* 8. Normal operation */
- PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n");
+ PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n");
do_ram_command(dev, RAM_COMMAND_NORMAL);
read32(rank_address + 0x30);
}
diff --git a/src/northbridge/via/cx700/cx700_early_smbus.c b/src/northbridge/via/cx700/cx700_early_smbus.c
index ccee3b4633..361b5e9bca 100644
--- a/src/northbridge/via/cx700/cx700_early_smbus.c
+++ b/src/northbridge/via/cx700/cx700_early_smbus.c
@@ -66,25 +66,25 @@ static void smbus_print_error(unsigned char host_status_register, int loops)
print_err("SMBus Error: ");
print_err_hex8(host_status_register);
- print_err("\r\n");
+ print_err("\n");
if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\r\n");
+ print_err("SMBus Timout\n");
}
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
+ print_err("Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\r\n");
+ print_err("Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\r\n");
+ print_err("Device Error\n");
}
if (host_status_register & (1 << 1)) {
/* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\r\n");
+ print_debug("Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\r\n");
+ print_err("Host Busy\n");
}
}
@@ -240,7 +240,7 @@ static void dump_spd_data(const struct mem_controller *ctrl)
for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
print_debug("SPD Data for DIMM ");
print_debug_hex8(dimm);
- print_debug("\r\n");
+ print_debug("\n");
val = get_spd_data(ctrl, dimm, 0);
if (val == 0xff) {
@@ -248,7 +248,7 @@ static void dump_spd_data(const struct mem_controller *ctrl)
} else if (val == 0x80) {
regs = 128;
} else {
- print_debug("No DIMM present\r\n");
+ print_debug("No DIMM present\n");
regs = 0;
}
for (offset = 0; offset < regs; offset++) {
@@ -256,7 +256,7 @@ static void dump_spd_data(const struct mem_controller *ctrl)
print_debug_hex8(offset);
print_debug(" = 0x");
print_debug_hex8(get_spd_data(ctrl, dimm, offset));
- print_debug("\r\n");
+ print_debug("\n");
}
}
}
diff --git a/src/northbridge/via/vt8601/raminit.c b/src/northbridge/via/vt8601/raminit.c
index 65c8088e68..2042d62d27 100644
--- a/src/northbridge/via/vt8601/raminit.c
+++ b/src/northbridge/via/vt8601/raminit.c
@@ -79,7 +79,7 @@ void dumpnorth(device_t north)
print_debug_hex8(pci_read_config8(north, r + c));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
if (r >= 240)
break;
}
@@ -90,13 +90,13 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
device_t north = (device_t) PCI_DEV(0, 0, 0);
uint8_t c, r;
- print_err("vt8601 init starting\r\n");
+ print_err("vt8601 init starting\n");
print_debug_hex32(north);
print_debug(" is the north\n");
print_debug_hex16(pci_read_config16(north, 0));
print_debug(" ");
print_debug_hex16(pci_read_config16(north, 2));
- print_debug("\r\n");
+ print_debug("\n");
/* All we are doing now is setting initial known-good values that will
* be revised later as we read SPD
@@ -186,7 +186,7 @@ static unsigned long spd_module_size(unsigned char slot)
print_info("Slot ");
print_info_hex8(slot);
if (smbus_read_byte(module, 2) != 4) {
- print_info(" is empty\r\n");
+ print_info(" is empty\n");
return 0;
}
print_info(" is SDRAM ");
@@ -211,7 +211,7 @@ static unsigned long spd_module_size(unsigned char slot)
print_info("x2");
value = (value << 16) | value;
}
- print_info("\r\n");
+ print_info("\n");
return value;
}
@@ -288,19 +288,19 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* set NOP */
pci_write_config8(north, 0x6C, 0x01);
- print_debug("NOP\r\n");
+ print_debug("NOP\n");
/* wait 200us */
// You need to do the memory reference. That causes the nop cycle.
dimms_read(0);
udelay(400);
- print_debug("PRECHARGE\r\n");
+ print_debug("PRECHARGE\n");
/* set precharge */
pci_write_config8(north, 0x6C, 0x02);
- print_debug("DUMMY READS\r\n");
+ print_debug("DUMMY READS\n");
/* dummy reads */
dimms_read(0);
udelay(200);
- print_debug("CBR\r\n");
+ print_debug("CBR\n");
/* set CBR */
pci_write_config8(north, 0x6C, 0x04);
@@ -321,7 +321,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
udelay(200);
dimms_read(0);
udelay(200);
- print_debug("MRS\r\n");
+ print_debug("MRS\n");
/* set MRS */
pci_write_config8(north, 0x6c, 0x03);
#if DIMM_CL2
@@ -330,21 +330,21 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dimms_read(0x1d0);
#endif
udelay(200);
- print_debug("NORMAL\r\n");
+ print_debug("NORMAL\n");
/* set to normal mode */
pci_write_config8(north, 0x6C, 0x08);
dimms_write(0x55aa55aa);
dimms_read(0);
udelay(200);
- print_debug("set ref. rate\r\n");
+ print_debug("set ref. rate\n");
// Set the refresh rate.
#if DIMM_PC133
pci_write_config8(north, 0x6A, 0x86);
#else
pci_write_config8(north, 0x6A, 0x65);
#endif
- print_debug("enable multi-page open\r\n");
+ print_debug("enable multi-page open\n");
// enable multi-page open
pci_write_config8(north, 0x6B, 0x0d);
@@ -381,8 +381,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
else /* 256MB or more per side */
ma = 0xe;
print_debug_hex16(ma);
- print_debug(" is the MA type\r\n");
+ print_debug(" is the MA type\n");
set_ma_mapping(north, slot, ma);
}
- print_err("vt8601 done\r\n");
+ print_err("vt8601 done\n");
}
diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c
index ffae808936..40338dae7e 100644
--- a/src/northbridge/via/vt8623/raminit.c
+++ b/src/northbridge/via/vt8623/raminit.c
@@ -56,7 +56,7 @@ dumpnorth(device_t north)
print_debug_hex8(pci_read_config8(north, r+c));
print_debug(" ");
}
- print_debug("\r\n");
+ print_debug("\n");
}
}
void print_val(char *str, int val)
@@ -72,7 +72,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
uint16_t i,j;
unsigned long bank_address;
- print_debug("vt8623 init starting\r\n");
+ print_debug("vt8623 init starting\n");
north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
north = 0;
@@ -102,7 +102,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
*/
c = 0;
b = smbus_read_byte(0xa0,17);
- print_val("Detecting Memory\r\nNumber of Banks ",b);
+ print_val("Detecting Memory\nNumber of Banks ",b);
if( b != 2 ){ // not 16 Mb type
@@ -110,14 +110,14 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Read SPD byte 3, Number of row addresses.
*/
b = smbus_read_byte(0xa0,3);
- print_val("\r\nNumber of Rows ",b);
+ print_val("\nNumber of Rows ",b);
if( b >= 0x0d ){ // not 64/128Mb (rows <=12)
/*
Read SPD byte 13, Primary DRAM width.
*/
b = smbus_read_byte(0xa0,13);
- print_val("\r\nPriamry DRAM width",b);
+ print_val("\nPriamry DRAM width",b);
if( b != 4 ) // mot 64/128Mb (x4)
c = 0x80; // 256Mb
}
@@ -128,13 +128,13 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
Read SPD byte 4, Number of column addresses.
*/
b = smbus_read_byte(0xa0,4);
- print_val("\r\nNo Columns ",b);
+ print_val("\nNo Columns ",b);
if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr
if( b == 9 ) c |= 0x40; // 9 bit col addr
if( b == 8 ) c |= 0x20; // 8 bit col addr
}
- print_val("\r\nMA type ",c);
+ print_val("\nMA type ",c);
pci_write_config8(north,0x58,c);
/*
@@ -161,18 +161,18 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
else c = 0x01; // Error, use default
- print_val("\r\nBank 0 (*16 Mb) ",c);
+ print_val("\nBank 0 (*16 Mb) ",c);
// set bank zero size
pci_write_config8(north,0x5a,c);
// SPD byte 5 # of physical banks
b = smbus_read_byte(0xa0,5);
- print_val("\r\nNo Physical Banks ",b);
+ print_val("\nNo Physical Banks ",b);
if( b == 2)
c <<=1;
- print_val("\r\nTotal Memory (*16 Mb) ",c);
+ print_val("\nTotal Memory (*16 Mb) ",c);
// set banks 1,2,3
pci_write_config8(north,0x5b,c);
pci_write_config8(north,0x5c,c);
@@ -181,40 +181,40 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
/* Read SPD byte 18 CAS Latency */
b = smbus_read_byte(0xa0,18);
- print_debug("\r\nCAS Supported ");
+ print_debug("\nCAS Supported ");
if(b & 0x04)
print_debug("2 ");
if(b & 0x08)
print_debug("2.5 ");
if(b & 0x10)
print_debug("3");
- print_val("\r\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9));
- print_val("\r\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
- print_val("\r\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25));
+ print_val("\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9));
+ print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
+ print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25));
if( b & 0x10 ){ // DDR offering optional CAS 3
- print_debug("\r\nStarting at CAS 3");
+ print_debug("\nStarting at CAS 3");
c = 0x30;
/* see if we can better it */
if( b & 0x08 ){ // DDR mandatory CAS 2.5
if( smbus_read_byte(0xa0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
- print_debug("\r\nWe can do CAS 2.5");
+ print_debug("\nWe can do CAS 2.5");
c = 0x20;
}
}
if( b & 0x04 ){ // DDR mandatory CAS 2
if( smbus_read_byte(0xa0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
- print_debug("\r\nWe can do CAS 2");
+ print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
}else{ // no optional CAS values just 2 & 2.5
- print_debug("\r\nStarting at CAS 2.5");
+ print_debug("\nStarting at CAS 2.5");
c = 0x20; // assume CAS 2.5
if( b & 0x04){ // Should always happen
if( smbus_read_byte(0xa0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
- print_debug("\r\nWe can do CAS 2");
+ print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
@@ -254,7 +254,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
*/
b = smbus_read_byte(0xa0,27);
- print_val("\r\ntRP ",b);
+ print_val("\ntRP ",b);
if( b > 0x3c ) // set tRP = 3T
c |= 0x80;
@@ -266,7 +266,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
*/
b = smbus_read_byte(0xa0,29);
- print_val("\r\ntRCD ",b);
+ print_val("\ntRCD ",b);
if( b > 0x3c ) // set tRCD = 3T
c |= 0x04;
@@ -278,7 +278,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
*/
b = smbus_read_byte(0xa0,30);
- print_val("\r\ntRAS ",b);
+ print_val("\ntRAS ",b);
if( b > 0x25 ) // set tRAS = 6T
c |= 0x40;
@@ -500,7 +500,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
break;
}
- print_val("\r\nLow Bond ",i);
+ print_val("\nLow Bond ",i);
if( i < 0xff ){
c = i++;
for( ; i <0xff ; i++){
@@ -549,7 +549,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
pci_write_config8(north,0x68,c);
pci_write_config8(north,0x68,0x42);
}else{
- print_debug("Unable to determine low bond - Setting default\r\n");
+ print_debug("Unable to determine low bond - Setting default\n");
pci_write_config8(north,0x68,0x59);
}
@@ -608,10 +608,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
pci_write_config8(north,0xac,0x2f);
pci_write_config8(north,0xae,0x04);
- print_debug("vt8623 done\r\n");
+ print_debug("vt8623 done\n");
dumpnorth(north);
- print_debug("AGP\r\n");
+ print_debug("AGP\n");
north = pci_locate_device(PCI_ID(0x1106, 0xb091), 0);
pci_write_config32(north,0x20,0xddf0dc00);
pci_write_config32(north,0x24,0xdbf0d800);
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 80ee22c22a..22c0fbd40f 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -52,13 +52,13 @@ int acpi_is_wakeup_early_via_vx800(void)
device_t dev;
u16 tmp, result;
- print_debug("In acpi_is_wakeup_early_via_vx800\r\n");
+ print_debug("In acpi_is_wakeup_early_via_vx800\n");
/* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX855_LPC), 0);
if (dev == PCI_DEV_INVALID)
- die("Power management controller not found\r\n");
+ die("Power management controller not found\n");
/* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1);
@@ -70,7 +70,7 @@ int acpi_is_wakeup_early_via_vx800(void)
result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
print_debug(" boot_mode=");
print_debug_hex16(result);
- print_debug("\r\n");
+ print_debug("\n");
return result;
}
@@ -85,7 +85,7 @@ static void enable_mainboard_devices(void)
device_t dev;
uint16_t values;
- print_debug("In enable_mainboard_devices \r\n");
+ print_debug("In enable_mainboard_devices \n");
/*
Enable P2P Bridge Header for External PCI BUS.
@@ -375,14 +375,14 @@ g) Rx73h = 32h
if (bist == 0) {
// CAR need mtrr untill mem is ok, so i disable this early_mtrr_init();
- //print_debug("doing early_mtrr\r\n");
+ //print_debug("doing early_mtrr\n");
//early_mtrr_init();
}
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\r\n");
+ print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
u8 Data;
@@ -392,7 +392,7 @@ g) Rx73h = 32h
Data = pci_read_config8(device, 0xf6);
print_debug("NB chip revision =");
print_debug_hex8(Data);
- print_debug("\r\n");
+ print_debug("\n");
/* make NB ready before draminit */
via_pci_inittable(Data, mNbStage1InitTbl);
@@ -405,7 +405,7 @@ g) Rx73h = 32h
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
DRAM_SYS_ATTR DramAttr;
- print_debug("This is a S3 wakeup\r\n");
+ print_debug("This is a S3 wakeup\n");
memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR));
/*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */
@@ -429,7 +429,7 @@ g) Rx73h = 32h
DRAMRegFinalValue(&DramAttr); // I just copy this function from draminit to here!
SetUMARam(); // I just copy this function from draminit to here!
- print_debug("Resume from S3, RAM init was ignored\r\n");
+ print_debug("Resume from S3, RAM init was ignored\n");
} else {
ddr2_ram_setup();
ram_check(0, 640 * 1024);
@@ -528,7 +528,7 @@ g) Rx73h = 32h
"rep movsd\n\t"
::"g"(memtop4)
);*/
- print_debug("copy memory to high memory to protect s3 wakeup vector code \r\n"); //this can have function call, because no variable used before this
+ print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this
memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) -
64 * 1024 - 0x100000),
(unsigned char *) 0, 0xa0000);
@@ -572,11 +572,11 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav
__asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)
);
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp);
+ printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
#else
print_debug("v_esp=");
print_debug_hex32(v_esp);
- print_debug("\r\n");
+ print_debug("\n");
#endif
}
@@ -588,11 +588,11 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav
//stack
cpu_reset = 0;
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset);
+ printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset);
#else
print_debug("cpu_reset = ");
print_debug_hex32(cpu_reset);
- print_debug("\r\n");
+ print_debug("\n");
#endif
if (cpu_reset == 0) {
@@ -635,16 +635,16 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav
/* We can not go back any more, we lost old stack data in cache as ram */
if (new_cpu_reset == 0) {
- print_debug("Use Ram as Stack now - done\r\n");
+ print_debug("Use Ram as Stack now - done\n");
} else {
- print_debug("Use Ram as Stack now - \r\n");
+ print_debug("Use Ram as Stack now - \n");
}
#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset);
+ printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = ");
print_debug_hex32(new_cpu_reset);
- print_debug("\r\n");
+ print_debug("\n");
#endif
/*copy and execute coreboot_ram */
copy_and_run(new_cpu_reset);
@@ -653,6 +653,6 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav
#endif
- print_debug("should not be here -\r\n");
+ print_debug("should not be here -\n");
}
diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c
index 58d70c33c3..ee010a0c8b 100644
--- a/src/northbridge/via/vx800/vga.c
+++ b/src/northbridge/via/vx800/vga.c
@@ -102,7 +102,7 @@ static void vga_init(device_t dev)
}
#else
/* Attempt to manually force the rom to load */
- printk(BIOS_DEBUG, "Forcing rom load\r\n");
+ printk(BIOS_DEBUG, "Forcing rom load\n");
pci_rom_load(dev, 0xfff80000);
run_bios(dev, 0xc0000);
#endif
diff --git a/src/northbridge/via/vx800/vx800_early_smbus.c b/src/northbridge/via/vx800/vx800_early_smbus.c
index 9beb9cf130..93b1461e9a 100644
--- a/src/northbridge/via/vx800/vx800_early_smbus.c
+++ b/src/northbridge/via/vx800/vx800_early_smbus.c
@@ -60,32 +60,32 @@
/* Internal functions */
static void smbus_print_error(unsigned char host_status_register, int loops)
{
-// print_err("some i2c error\r\n");
+// print_err("some i2c error\n");
/* Check if there actually was an error */
if (host_status_register == 0x00 || host_status_register == 0x40 ||
host_status_register == 0x42)
return;
print_err("smbus_error: ");
print_err_hex8(host_status_register);
- print_err("\r\n");
+ print_err("\n");
if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\r\n");
+ print_err("SMBus Timout\n");
}
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
+ print_err("Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\r\n");
+ print_err("Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\r\n");
+ print_err("Device Error\n");
}
if (host_status_register & (1 << 1)) {
/* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\r\n");
+ print_debug("Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\r\n");
+ print_err("Host Busy\n");
}
}
@@ -204,7 +204,7 @@ static void enable_smbus(void)
if (dev == PCI_DEV_INVALID) {
/* This won't display text if enable_smbus() is before serial init */
- die("Power Managment Controller not found\r\n");
+ die("Power Managment Controller not found\n");
}
/* Set clock source */
@@ -253,7 +253,7 @@ void smbus_fixup(const struct mem_controller *ctrl)
ram_slots = ARRAY_SIZE(ctrl->channel0);
if (!ram_slots) {
- print_err("smbus_fixup() thinks there are no RAM slots!\r\n");
+ print_err("smbus_fixup() thinks there are no RAM slots!\n");
return;
}
@@ -279,9 +279,9 @@ void smbus_fixup(const struct mem_controller *ctrl)
}
if (i >= SMBUS_TIMEOUT)
- print_err("SMBus timed out while warming up\r\n");
+ print_err("SMBus timed out while warming up\n");
else
- PRINT_DEBUG("Done\r\n");
+ PRINT_DEBUG("Done\n");
}
/* Debugging Function */
@@ -294,7 +294,7 @@ static void dump_spd_data(void)
for (dimm = 0; dimm < 8; dimm++) {
print_debug("SPD Data for DIMM ");
print_debug_hex8(dimm);
- print_debug("\r\n");
+ print_debug("\n");
val = get_spd_data(dimm, 0);
if (val == 0xff) {
@@ -302,7 +302,7 @@ static void dump_spd_data(void)
} else if (val == 0x80) {
regs = 128;
} else {
- print_debug("No DIMM present\r\n");
+ print_debug("No DIMM present\n");
regs = 0;
}
for (offset = 0; offset < regs; offset++) {
@@ -310,7 +310,7 @@ static void dump_spd_data(void)
print_debug_hex8(offset);
print_debug(" = 0x");
print_debug_hex8(get_spd_data(dimm, offset));
- print_debug("\r\n");
+ print_debug("\n");
}
}
}