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-rw-r--r--src/northbridge/amd/lx/Makefile.inc1
-rw-r--r--src/northbridge/amd/lx/generic_sdram.c29
2 files changed, 30 insertions, 0 deletions
diff --git a/src/northbridge/amd/lx/Makefile.inc b/src/northbridge/amd/lx/Makefile.inc
index 19d9e44db6..190c0598e4 100644
--- a/src/northbridge/amd/lx/Makefile.inc
+++ b/src/northbridge/amd/lx/Makefile.inc
@@ -5,5 +5,6 @@ ramstage-y += northbridgeinit.c
ramstage-y += grphinit.c
romstage-y += raminit.c
+romstage-y += generic_sdram.c
endif
diff --git a/src/northbridge/amd/lx/generic_sdram.c b/src/northbridge/amd/lx/generic_sdram.c
new file mode 100644
index 0000000000..21239c6c17
--- /dev/null
+++ b/src/northbridge/amd/lx/generic_sdram.c
@@ -0,0 +1,29 @@
+#include <console/console.h>
+#include <northbridge/amd/lx/raminit.h>
+
+/* Setup SDRAM */
+void sdram_initialize(int controllers, const struct mem_controller *ctrl)
+{
+ int i;
+ /* Set the registers we can set once to reasonable values */
+ for (i = 0; i < controllers; i++) {
+ printk(BIOS_DEBUG, "Ram1.%02x\n", i);
+ sdram_set_registers(ctrl + i);
+ }
+
+ /* Now setup those things we can auto detect */
+ for (i = 0; i < controllers; i++) {
+ printk(BIOS_DEBUG, "Ram2.%02x\n", i);
+ sdram_set_spd_registers(ctrl + i);
+ }
+
+ /* Now that everything is setup enable the SDRAM.
+ * Some chipsets do the work for us while on others
+ * we need to it by hand.
+ */
+ printk(BIOS_DEBUG, "Ram3\n");
+
+ sdram_enable(controllers, ctrl);
+
+ printk(BIOS_DEBUG, "Ram4\n");
+}