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-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c4
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.h4
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c7
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c20
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c6
5 files changed, 21 insertions, 20 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 4615dd2ed0..9850d9bc2c 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -3798,7 +3798,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
reg = 0x78;
val = Get_NB32_DCT(dev, Channel, reg);
val &= ~(0x3ff<<22);
- val |= ((u32) pDCTstat->CH_MaxRdLat[Channel] << 22);
+ val |= ((u32) pDCTstat->CH_MaxRdLat[Channel][0] << 22);
val &= ~(1<<DqsRcvEnTrain);
Set_NB32_DCT(dev, Channel, reg, val); /* program MaxRdLatency to correspond with current delay*/
}
@@ -7391,7 +7391,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
p = (u8 *) pDCTstat;
start = 0;
- stop = ((u32) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2]);
+ stop = ((u32) &((struct DCTStatStruc *)0)->CH_D_DIR_B_DQS);
for (i = start; i < stop ; i++) {
p[i] = 0;
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index 654acc0b32..fd35f9c2c9 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2015-2016 Raptor Engineering, LLC
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -498,7 +498,7 @@ struct DCTStatStruc { /* A per Node structure*/
u16 CSUsrTestFail; /* Chip selects excluded by user */
/* DCTStatStruct_F - end */
- u16 CH_MaxRdLat[2]; /* Max Read Latency (ns) for DCT 0*/
+ u16 CH_MaxRdLat[2][2]; /* Max Read Latency (nclks) [dct][pstate] */
/* Max Read Latency (ns) for DCT 1*/
u8 CH_D_DIR_B_DQS[2][4][2][9]; /* [A/B] [DIMM1-4] [R/W] [DQS] */
/* CHA DIMM0 Byte 0 - 7 and Check Write DQS Delay*/
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 5d75fb0392..a9097eaf5b 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -877,7 +877,8 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat,
mem_clk = Get_NB32_DCT(dev, dct, 0x94) & 0x1f;
if (fam15h_freq_tab[mem_clk] == 0) {
- pDCTstat->CH_MaxRdLat[dct] = 0x55;
+ pDCTstat->CH_MaxRdLat[dct][0] = 0x55;
+ pDCTstat->CH_MaxRdLat[dct][1] = 0x55;
return;
}
@@ -947,10 +948,10 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat,
}
/* Save result for later use */
- pDCTstat->CH_MaxRdLat[dct] = n - 1;
+ pDCTstat->CH_MaxRdLat[dct][nb_pstate] = n - 1;
#if DQS_TRAIN_DEBUG > 0
- printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d]: %03x\n", __func__, dct, pDCTstat->CH_MaxRdLat[dct]);
+ printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d][%d]: %03x\n", __func__, dct, nb_pstate, pDCTstat->CH_MaxRdLat[dct][nb_pstate]);
#endif
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 9a0d372528..524bea00e7 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -998,7 +998,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n");
for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) {
printk(BIOS_DEBUG, "Channel:%x: %x\n",
- ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]);
+ ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]);
}
}
#endif
@@ -1498,7 +1498,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n");
for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) {
printk(BIOS_DEBUG, "Channel:%x: %x\n",
- ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]);
+ ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]);
}
}
#endif
@@ -1533,7 +1533,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
}
static void write_max_read_latency_to_registers(struct MCTStatStruc *pMCTstat,
- struct DCTStatStruc *pDCTstat, uint8_t dct, uint16_t latency)
+ struct DCTStatStruc *pDCTstat, uint8_t dct, uint16_t *latency)
{
uint32_t dword;
uint8_t nb_pstate;
@@ -1541,7 +1541,7 @@ static void write_max_read_latency_to_registers(struct MCTStatStruc *pMCTstat,
for (nb_pstate = 0; nb_pstate < 2; nb_pstate++) {
dword = Get_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210);
dword &= ~(0x3ff << 22);
- dword |= ((latency & 0x3ff) << 22);
+ dword |= ((latency[nb_pstate] & 0x3ff) << 22);
Set_NB32_DCT_NBPstate(pDCTstat->dev_dct, dct, nb_pstate, 0x210, dword);
}
}
@@ -1665,7 +1665,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
/* 2.10.5.8.5.1.4
* Incrementally test each MaxRdLatency candidate
*/
- for (; pDCTstat->CH_MaxRdLat[Channel] < 0x3ff; pDCTstat->CH_MaxRdLat[Channel]++) {
+ for (; pDCTstat->CH_MaxRdLat[Channel][0] < 0x3ff; pDCTstat->CH_MaxRdLat[Channel][0]++) {
write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]);
read_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff, 0);
dword = Get_NB32_DCT(dev, Channel, 0x268) & 0x3ffff;
@@ -1683,8 +1683,8 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
dword = Get_NB32(pDCTstat->dev_nbctl, (0x160 + (nb_pstate * 4))); /* Retrieve NbDid, NbFid */
nb_clk = (200 * (((dword >> 1) & 0x1f) + 0x4)) / (((dword >> 7) & 0x1)?2:1);
- pDCTstat->CH_MaxRdLat[Channel]++;
- pDCTstat->CH_MaxRdLat[Channel] += ((((uint64_t)15 * 100000000000ULL) / ((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL))
+ pDCTstat->CH_MaxRdLat[Channel][0]++;
+ pDCTstat->CH_MaxRdLat[Channel][0] += ((((uint64_t)15 * 100000000000ULL) / ((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL))
* ((uint64_t)nb_clk * 1000)) / 1000000000ULL;
write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]);
@@ -1712,7 +1712,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
printk(BIOS_DEBUG, "TrainMaxRdLatency: CH_MaxRdLat:\n");
for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) {
printk(BIOS_DEBUG, "Channel:%x: %x\n",
- ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]);
+ ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]);
}
}
#endif
@@ -1904,9 +1904,9 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
*/
SubTotal += (cpu_val_n) / 2;
- pDCTstat->CH_MaxRdLat[Channel] = SubTotal;
+ pDCTstat->CH_MaxRdLat[Channel][0] = SubTotal;
if(pDCTstat->GangedMode) {
- pDCTstat->CH_MaxRdLat[1] = SubTotal;
+ pDCTstat->CH_MaxRdLat[1][0] = SubTotal;
}
/* Program the F2x[1, 0]78[MaxRdLatency] register with
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
index 1b18efa259..8cda2f8db0 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
@@ -191,7 +191,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
u8 ChannelDTD;
printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n");
for(ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) {
- printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD]);
+ printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]);
}
}
#endif
@@ -208,9 +208,9 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat,
if (pDCTstat->GangedMode) {
Channel = 0; /* for safe */
for (i=0; i<2; i++)
- pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
+ pDCTstat->CH_MaxRdLat[i][0] = MaxRdLatVal;
} else {
- pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal;
+ pDCTstat->CH_MaxRdLat[Channel][0] = MaxRdLatVal;
}
dev = pDCTstat->dev_dct;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 00:53:39 +0000