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-rw-r--r--src/northbridge/intel/e7505/memmap.c4
-rw-r--r--src/northbridge/intel/gm45/ram_calc.c4
-rw-r--r--src/northbridge/intel/i440bx/ram_calc.c5
-rw-r--r--src/northbridge/intel/i945/ram_calc.c4
-rw-r--r--src/northbridge/intel/nehalem/ram_calc.c4
-rw-r--r--src/northbridge/intel/pineview/ram_calc.c5
-rw-r--r--src/northbridge/intel/sandybridge/ram_calc.c4
-rw-r--r--src/northbridge/intel/x4x/ram_calc.c4
8 files changed, 10 insertions, 24 deletions
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index f7a08bc28d..d45006566e 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -35,8 +35,6 @@ void *cbmem_top(void)
return (void *)tolm;
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
@@ -45,7 +43,7 @@ void platform_enter_postcar(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/*
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index c1307c48f5..c6140824f0 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -123,8 +123,6 @@ void *cbmem_top(void)
return (void *) top_of_ram;
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
@@ -133,7 +131,7 @@ void platform_enter_postcar(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c
index 09a3b03272..495ca8682a 100644
--- a/src/northbridge/intel/i440bx/ram_calc.c
+++ b/src/northbridge/intel/i440bx/ram_calc.c
@@ -15,6 +15,7 @@
#define __SIMPLE_DEVICE__
+#include <arch/cpu.h>
#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
@@ -67,8 +68,6 @@ void *cbmem_top(void)
return (void *)tom;
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
@@ -77,7 +76,7 @@ void platform_enter_postcar(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 752c8f901c..525a5b9c0e 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -88,8 +88,6 @@ u32 decode_igd_memory_size(const u32 gms)
return ggc2uma[gms] << 10;
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
@@ -98,7 +96,7 @@ void platform_enter_postcar(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index e32190f519..ba3761065b 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -43,8 +43,6 @@ void *cbmem_top(void)
return (void *) smm_region_start();
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
@@ -53,7 +51,7 @@ void platform_enter_postcar(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index a789956ea3..d1b43aa42d 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -16,6 +16,7 @@
#define __SIMPLE_DEVICE__
+#include <arch/cpu.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci_def.h>
@@ -137,8 +138,6 @@ void *cbmem_top(void)
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
@@ -147,7 +146,7 @@ void platform_enter_postcar(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
index 5cda8a33fe..343ae62711 100644
--- a/src/northbridge/intel/sandybridge/ram_calc.c
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -43,8 +43,6 @@ void *cbmem_top(void)
return (void *) smm_region_start();
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
@@ -53,7 +51,7 @@ void platform_enter_postcar(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 371496985f..be9c10f001 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -134,8 +134,6 @@ void *cbmem_top(void)
return (void *) top_of_ram;
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
@@ -144,7 +142,7 @@ void platform_enter_postcar(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 13:05:07 +0000