5 files changed, 26 insertions, 27 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index ade120f442..f4d091696e 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -23,6 +23,7 @@
 #include <halt.h>
 #include <string.h>
 #include "i945.h"
+#include <pc80/mc146818rtc.h>
 
 int i945_silicon_revision(void)
 {
@@ -145,7 +146,7 @@ static void i945_detect_chipset(void)
 
 static void i945_setup_bars(void)
 {
-	u8 reg8;
+	u8 reg8, gfxsize;
 
 	/* As of now, we don't have all the A0 workarounds implemented */
 	if (i945_silicon_revision() == 0)
@@ -178,10 +179,13 @@ static void i945_setup_bars(void)
 	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
 	pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
 
-	/* Hardware default is 8MB UMA. If someone wants to make this a
-	 * CMOS or compile time option, send a patch.
-	 * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30);
-	 */
+	/* vram size from cmos option */
+	if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS)
+		gfxsize = 2;	/* 2 for 8MB */
+	/* make sure no invalid setting is used */
+	if (gfxsize > 6)
+		gfxsize = 2;
+	pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4));
 
 	/* Set C0000-FFFFF to access RAM on both reads and writes */
 	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index df13ef4950..02caa0a37a 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -353,17 +353,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
 	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
 	uma_size = 0;
 	if (!(reg16 & 2)) {
-		reg16 >>= 4;
-		reg16 &= 7;
-		switch (reg16) {
-		case 1:
-			uma_size = 1024;
-			break;
-		case 3:
-			uma_size = 8192;
-			break;
-		}
-
+		uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
 		printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
 	}
 
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 0536a36d71..a7a3c5ccd3 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -364,6 +364,8 @@ void dump_pci_devices(void);
 void dump_spd_registers(void);
 void dump_mem(unsigned start, unsigned end);
 
+u32 decode_igd_memory_size(u32 gms);
+
 #endif /* __ACPI__ */
 
 #endif /* NORTHBRIDGE_INTEL_I945_H */
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 514f88c8af..719a7954f2 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -104,18 +104,8 @@ static void pci_domain_set_resources(device_t dev)
 	/* Note: subtract IGD device and TSEG */
 	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
 	if (!(reg16 & 2)) {
-		int uma_size = 0;
 		printk(BIOS_DEBUG, "IGD decoded, subtracting ");
-		reg16 >>= 4;
-		reg16 &= 7;
-		switch (reg16) {
-		case 1:
-			uma_size = 1024;
-			break;
-		case 3:
-			uma_size = 8192;
-			break;
-		}
+		int uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
 
 		printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
 		tomk_stolen -= uma_size;
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index b161431e15..4349d19ea7 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -19,6 +19,7 @@
 #include <arch/io.h>
 #include <cbmem.h>
 #include "i945.h"
+#include <console/console.h>
 
 static uintptr_t smm_region_start(void)
 {
@@ -56,3 +57,15 @@ void *cbmem_top(void)
 {
 	return (void *) smm_region_start();
 }
+
+/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
+u32 decode_igd_memory_size(const u32 gms)
+{
+	static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32,
+			48, 64 };
+
+	if (gms > ARRAY_SIZE(ggc2uma))
+		die("Bad Graphics Mode Select (GMS) setting.\n");
+
+	return ggc2uma[gms] << 10;
+}