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-rw-r--r--src/northbridge/amd/gx2/pll_reset.c5
-rw-r--r--src/northbridge/amd/lx/pll_reset.c3
2 files changed, 3 insertions, 5 deletions
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c
index 1f3c65dcbe..7b8694b690 100644
--- a/src/northbridge/amd/gx2/pll_reset.c
+++ b/src/northbridge/amd/gx2/pll_reset.c
@@ -78,9 +78,8 @@ static void pll_reset(void)
} else if (CONFIG_GX2_PROCESSOR_MHZ == 300) {
DEFAULT_FBDIV = 18;
} else {
- printk(BIOS_ERR, "Unsupported GX2_PROCESSOR_MHZ setting!\n");
post_code(POST_PLL_CPU_VER_FAIL);
- __asm__ __volatile__("hlt\n");
+ die("Unsupported GX2_PROCESSOR_MHZ setting!\n");
}
/* clear the Bypass bit */
@@ -186,7 +185,7 @@ static void pll_reset(void)
/* You should never get here..... The chip has reset. */
post_code(POST_PLL_RESET_FAIL);
- while (1);
+ die("CONFIGURING PLL FAILURE\n");
} /* we haven't configured the PLL; do it now */
diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index 1f8e499825..3077b61c9c 100644
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -59,9 +59,8 @@ static void pll_reset(char manualconf)
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
/* You should never get here..... The chip has reset. */
- printk(BIOS_ERR, "CONFIGURING PLL FAILURE\n");
post_code(POST_PLL_RESET_FAIL);
- __asm__ __volatile__("hlt\n");
+ die("CONFIGURING PLL FAILURE\n");
}
printk(BIOS_DEBUG, "PLL configured.\n");