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-rw-r--r--src/northbridge/intel/ironlake/quickpath.c105
-rw-r--r--src/northbridge/intel/ironlake/raminit.c104
-rw-r--r--src/northbridge/intel/ironlake/raminit.h1
3 files changed, 107 insertions, 103 deletions
diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c
index 44e330cb5a..068afeb5b2 100644
--- a/src/northbridge/intel/ironlake/quickpath.c
+++ b/src/northbridge/intel/ironlake/quickpath.c
@@ -429,6 +429,111 @@ static void set_2dxx_series(struct raminfo *info, int s3resume)
MCHBAR32(0x2db8) = ((info->fsb_frequency - 1) << 16) | 0x77;
}
+#define gav(x) (x)
+
+void early_quickpath_init(const u8 x2ca8)
+{
+ if (x2ca8 == 0) {
+ gav(MCHBAR8(0x164));
+ MCHBAR8(0x164) = 0x26;
+ MCHBAR16(0x2c20) = 0x10;
+ }
+
+ MCHBAR32_OR(0x18b4, 0x210000);
+ MCHBAR32_OR(0x1890, 0x2000000);
+ MCHBAR32_OR(0x18b4, 0x8000);
+
+ gav(pci_read_config32(QPI_PHY_0, QPI_PLL_STATUS)); // !!!!
+ pci_write_config8(QPI_PHY_0, QPI_PLL_RATIO, 0x12);
+
+ gav(MCHBAR16(0x2c10));
+ MCHBAR16(0x2c10) = 0x412;
+ gav(MCHBAR16(0x2c10));
+ MCHBAR16_OR(0x2c12, 0x100);
+
+ gav(MCHBAR8(0x2ca8)); // !!!!
+ MCHBAR32_AND_OR(0x1804, 0xfffffffc, 0x8400080);
+
+ pci_read_config32(QPI_PHY_0, QPI_PHY_CONTROL); // !!!!
+ pci_write_config32(QPI_PHY_0, QPI_PHY_CONTROL, 0x40a0a0);
+ gav(MCHBAR32(0x1c04)); // !!!!
+ gav(MCHBAR32(0x1804)); // !!!!
+
+ if (x2ca8 == 0)
+ MCHBAR8_OR(0x2ca8, 1);
+
+ MCHBAR32(0x18d8) = 0x120000;
+ MCHBAR32(0x18dc) = 0x30a484a;
+ pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x0);
+ pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9444a);
+ MCHBAR32(0x18d8) = 0x40000;
+ MCHBAR32(0x18dc) = 0xb000000;
+ pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x60000);
+ pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x0);
+ MCHBAR32(0x18d8) = 0x180000;
+ MCHBAR32(0x18dc) = 0xc0000142;
+ pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x20000);
+ pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x142);
+ MCHBAR32(0x18d8) = 0x1e0000;
+
+ gav(MCHBAR32(0x18dc)); // !!!!
+ MCHBAR32(0x18dc) = 0x3;
+ gav(MCHBAR32(0x18dc)); // !!!!
+
+ if (x2ca8 == 0)
+ MCHBAR8_OR(0x2ca8, 1); // guess
+
+ MCHBAR32(0x188c) = 0x20bc09;
+ pci_write_config32(QPI_PHY_0, QPI_PHY_PWR_MGMT, 0x40b0c09);
+ MCHBAR32(0x1a10) = 0x4200010e;
+ MCHBAR32_OR(0x18b8, 0x200);
+ gav(MCHBAR32(0x1918)); // !!!!
+ MCHBAR32(0x1918) = 0x332;
+
+ gav(MCHBAR32(0x18b8)); // !!!!
+ MCHBAR32(0x18b8) = 0xe00;
+ gav(MCHBAR32(0x182c)); // !!!!
+ MCHBAR32(0x182c) = 0x10202;
+ gav(pci_read_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT)); // !!!!
+ pci_write_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT, 0x10202);
+ MCHBAR32_AND(0x1a1c, 0x8fffffff);
+ MCHBAR32_OR(0x1a70, 0x100000);
+
+ MCHBAR32_AND(0x18b4, 0xffff7fff);
+ gav(MCHBAR32(0x1a68)); // !!!!
+ MCHBAR32(0x1a68) = 0x343800;
+ gav(MCHBAR32(0x1e68)); // !!!!
+ gav(MCHBAR32(0x1a68)); // !!!!
+
+ if (x2ca8 == 0)
+ MCHBAR8_OR(0x2ca8, 1); // guess
+
+ pci_read_config32(QPI_LINK_0, QPI_QPILCL); // !!!!
+ pci_write_config32(QPI_LINK_0, QPI_QPILCL, 0x140000);
+ pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!!
+ pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555);
+ pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!!
+ pci_read_config32(QPI_NON_CORE, MIRROR_PORT_CTL); // !!!!
+ pci_write_config32(QPI_NON_CORE, MIRROR_PORT_CTL, 0x180);
+ gav(MCHBAR32(0x1af0)); // !!!!
+ gav(MCHBAR32(0x1af0)); // !!!!
+ MCHBAR32(0x1af0) = 0x1f020003;
+ gav(MCHBAR32(0x1af0)); // !!!!
+
+ if (x2ca8 == 0)
+ MCHBAR8_OR(0x2ca8, 1); // guess
+
+ gav(MCHBAR32(0x1890)); // !!!!
+ MCHBAR32(0x1890) = 0x80102;
+ gav(MCHBAR32(0x18b4)); // !!!!
+ MCHBAR32(0x18b4) = 0x216000;
+ MCHBAR32(0x18a4) = 0x22222222;
+ MCHBAR32(0x18a8) = 0x22222222;
+ MCHBAR32(0x18ac) = 0x22222;
+
+ udelay(1000);
+}
+
void late_quickpath_init(struct raminfo *info, const int s3resume)
{
const u16 deven = pci_read_config16(NORTHBRIDGE, DEVEN);
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index 0efe1760fe..fb042d6057 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -3353,109 +3353,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
compute_derived_timings(&info);
- if (x2ca8 == 0) {
- gav(MCHBAR8(0x164));
- MCHBAR8(0x164) = 0x26;
- MCHBAR16(0x2c20) = 0x10;
- }
-
- MCHBAR32_OR(0x18b4, 0x210000);
- MCHBAR32_OR(0x1890, 0x2000000);
- MCHBAR32_OR(0x18b4, 0x8000);
-
- gav(pci_read_config32(QPI_PHY_0, QPI_PLL_STATUS)); // !!!!
- pci_write_config8(QPI_PHY_0, QPI_PLL_RATIO, 0x12);
-
- gav(MCHBAR16(0x2c10));
- MCHBAR16(0x2c10) = 0x412;
- gav(MCHBAR16(0x2c10));
- MCHBAR16_OR(0x2c12, 0x100);
-
- gav(MCHBAR8(0x2ca8)); // !!!!
- MCHBAR32_AND_OR(0x1804, 0xfffffffc, 0x8400080);
-
- pci_read_config32(QPI_PHY_0, QPI_PHY_CONTROL); // !!!!
- pci_write_config32(QPI_PHY_0, QPI_PHY_CONTROL, 0x40a0a0);
- gav(MCHBAR32(0x1c04)); // !!!!
- gav(MCHBAR32(0x1804)); // !!!!
-
- if (x2ca8 == 0) {
- MCHBAR8_OR(0x2ca8, 1);
- }
-
- MCHBAR32(0x18d8) = 0x120000;
- MCHBAR32(0x18dc) = 0x30a484a;
- pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x0);
- pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x9444a);
- MCHBAR32(0x18d8) = 0x40000;
- MCHBAR32(0x18dc) = 0xb000000;
- pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x60000);
- pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x0);
- MCHBAR32(0x18d8) = 0x180000;
- MCHBAR32(0x18dc) = 0xc0000142;
- pci_write_config32(QPI_PHY_0, QPI_PHY_EP_SELECT, 0x20000);
- pci_write_config32(QPI_PHY_0, QPI_PHY_EP_MCTR, 0x142);
- MCHBAR32(0x18d8) = 0x1e0000;
-
- gav(MCHBAR32(0x18dc)); // !!!!
- MCHBAR32(0x18dc) = 0x3;
- gav(MCHBAR32(0x18dc)); // !!!!
-
- if (x2ca8 == 0) {
- MCHBAR8_OR(0x2ca8, 1); // guess
- }
-
- MCHBAR32(0x188c) = 0x20bc09;
- pci_write_config32(QPI_PHY_0, QPI_PHY_PWR_MGMT, 0x40b0c09);
- MCHBAR32(0x1a10) = 0x4200010e;
- MCHBAR32_OR(0x18b8, 0x200);
- gav(MCHBAR32(0x1918)); // !!!!
- MCHBAR32(0x1918) = 0x332;
-
- gav(MCHBAR32(0x18b8)); // !!!!
- MCHBAR32(0x18b8) = 0xe00;
- gav(MCHBAR32(0x182c)); // !!!!
- MCHBAR32(0x182c) = 0x10202;
- gav(pci_read_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT)); // !!!!
- pci_write_config32(QPI_PHY_0, QPI_PHY_PRIM_TIMEOUT, 0x10202);
- MCHBAR32_AND(0x1a1c, 0x8fffffff);
- MCHBAR32_OR(0x1a70, 0x100000);
-
- MCHBAR32_AND(0x18b4, 0xffff7fff);
- gav(MCHBAR32(0x1a68)); // !!!!
- MCHBAR32(0x1a68) = 0x343800;
- gav(MCHBAR32(0x1e68)); // !!!!
- gav(MCHBAR32(0x1a68)); // !!!!
-
- if (x2ca8 == 0) {
- MCHBAR8_OR(0x2ca8, 1); // guess
- }
-
- pci_read_config32(QPI_LINK_0, QPI_QPILCL); // !!!!
- pci_write_config32(QPI_LINK_0, QPI_QPILCL, 0x140000);
- pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!!
- pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555);
- pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!!
- pci_read_config32(QPI_NON_CORE, MIRROR_PORT_CTL); // !!!!
- pci_write_config32(QPI_NON_CORE, MIRROR_PORT_CTL, 0x180);
- gav(MCHBAR32(0x1af0)); // !!!!
- gav(MCHBAR32(0x1af0)); // !!!!
- MCHBAR32(0x1af0) = 0x1f020003;
- gav(MCHBAR32(0x1af0)); // !!!!
-
- if (x2ca8 == 0) {
- MCHBAR8_OR(0x2ca8, 1); // guess
- }
-
- gav(MCHBAR32(0x1890)); // !!!!
- MCHBAR32(0x1890) = 0x80102;
- gav(MCHBAR32(0x18b4)); // !!!!
- MCHBAR32(0x18b4) = 0x216000;
- MCHBAR32(0x18a4) = 0x22222222;
- MCHBAR32(0x18a8) = 0x22222222;
- MCHBAR32(0x18ac) = 0x22222;
-
- udelay(1000);
+ early_quickpath_init(x2ca8);
info.cached_training = get_cached_training();
diff --git a/src/northbridge/intel/ironlake/raminit.h b/src/northbridge/intel/ironlake/raminit.h
index 9967e15140..e75fa5182b 100644
--- a/src/northbridge/intel/ironlake/raminit.h
+++ b/src/northbridge/intel/ironlake/raminit.h
@@ -103,6 +103,7 @@ void chipset_init(const int s3resume);
void raminit(const int s3resume, const u8 *spd_addrmap);
u16 get_max_timing(struct raminfo *info, int channel);
+void early_quickpath_init(const u8 x2ca8);
void late_quickpath_init(struct raminfo *info, const int s3resume);
#endif /* RAMINIT_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 14:55:17 +0000