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-rw-r--r--src/northbridge/via/vx900/chrome9hd.c28
-rw-r--r--src/northbridge/via/vx900/lpc.c18
-rw-r--r--src/northbridge/via/vx900/northbridge.c18
-rw-r--r--src/northbridge/via/vx900/pcie.c6
-rw-r--r--src/northbridge/via/vx900/sata.c16
-rw-r--r--src/northbridge/via/vx900/traf_ctrl.c8
6 files changed, 47 insertions, 47 deletions
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
index 00b5c4bb77..254be7b886 100644
--- a/src/northbridge/via/vx900/chrome9hd.c
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -98,7 +98,7 @@
u8 vx900_int15_get_5f18_bl(void)
{
u8 reg8, ret;
- device_t dev;
+ struct device *dev;
/*
* BL Bit[7:4]
* Memory Data Rate (not to be confused with fCLK)
@@ -137,7 +137,7 @@ static void chrome9hd_set_sid_vid(u16 vendor, u16 device)
vga_sr_write(0x37, device & 0xff); /* SID low byte */
}
-static void chrome9hd_handle_uma(device_t dev)
+static void chrome9hd_handle_uma(struct device *dev)
{
u8 fb_pow = vx900_get_chrome9hd_fb_pow();
@@ -165,12 +165,12 @@ static void chrome9hd_handle_uma(device_t dev)
*
* This document is only available under NDA.
*/
-static void chrome9hd_biosguide_init_seq(device_t dev)
+static void chrome9hd_biosguide_init_seq(struct device *dev)
{
- device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
- device_t host = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VX900_HOST_BR, 0);
+ struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
+ struct device *host = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_HOST_BR, 0);
/* Step 1 - Enable VGA controller */
/* FIXME: This is the VGA hole @ 640k-768k, and the vga port io
@@ -208,7 +208,7 @@ static void chrome9hd_biosguide_init_seq(device_t dev)
}
-static void chrome9hd_init(device_t dev)
+static void chrome9hd_init(struct device *dev)
{
printk(BIOS_DEBUG, "======================================================\n");
printk(BIOS_DEBUG, "== Chrome9 HD INIT\n");
@@ -243,18 +243,18 @@ static void chrome9hd_init(device_t dev)
dump_pci_device(dev);
}
-static void chrome9hd_enable(device_t dev)
+static void chrome9hd_enable(struct device *dev)
{
- device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
+ struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
/* FIXME: here? -=- ACLK 250MHz */
pci_mod_config8(mcu, 0xbb, 0, 0x01);
}
-static void chrome9hd_disable(device_t dev)
+static void chrome9hd_disable(struct device *dev)
{
- device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
+ struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
/* Disable GFX - This step effectively renders the GFX inert
* It won't even show up as a PCI device during enumeration */
pci_mod_config8(mcu, 0xa1, 1 << 7, 0);
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index 43e4d4c3b0..075a8723c7 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -47,7 +47,7 @@
* it will work, but perhaps this should be more configurable.
*/
-static void vx900_lpc_misc_stuff(device_t dev)
+static void vx900_lpc_misc_stuff(struct device *dev)
{
char extint;
u8 val;
@@ -71,7 +71,7 @@ static void vx900_lpc_misc_stuff(device_t dev)
}
}
-static void vx900_lpc_dma_setup(device_t dev)
+static void vx900_lpc_dma_setup(struct device *dev)
{
/* These are the steps recommended by VIA in order to get DMA running */
@@ -104,12 +104,12 @@ static void vx900_lpc_dma_setup(device_t dev)
* We are assuming this is called before the drivers/generic/ioapic code,
* which should be the case if devicetree.cb is set up properly.
*/
-static void vx900_lpc_ioapic_setup(device_t dev)
+static void vx900_lpc_ioapic_setup(struct device *dev)
{
/* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb
* If it's not, then the generic ioapic driver will not set it up
* correctly, and the MP table will not be correctly generated */
- device_t ioapic;
+ struct device *ioapic;
for (ioapic = dev->next; ioapic; ioapic = ioapic->next) {
if (ioapic->path.type == DEVICE_PATH_IOAPIC)
break;
@@ -151,7 +151,7 @@ static void vx900_lpc_ioapic_setup(device_t dev)
pci_mod_config8(dev, 0x58, 0, 1 << 6);
}
-static void vx900_lpc_interrupt_stuff(device_t dev)
+static void vx900_lpc_interrupt_stuff(struct device *dev)
{
/* Enable setting trigger mode through 0x4d0, and 0x4d1 ports
* And enable I/O recovery time */
@@ -177,14 +177,14 @@ static void vx900_lpc_interrupt_stuff(device_t dev)
vx900_lpc_ioapic_setup(dev);
}
-static void vx900_lpc_init(device_t dev)
+static void vx900_lpc_init(struct device *dev)
{
vx900_lpc_interrupt_stuff(dev);
vx900_lpc_misc_stuff(dev);
dump_pci_device(dev);
}
-static void vx900_lpc_read_resources(device_t dev)
+static void vx900_lpc_read_resources(struct device *dev)
{
struct resource *res;
pci_dev_read_resources(dev);
@@ -206,7 +206,7 @@ static void vx900_lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE;
}
-static void vx900_lpc_set_resources(device_t dev)
+static void vx900_lpc_set_resources(struct device *dev)
{
struct resource *mmio, *spi;
u32 reg;
@@ -248,7 +248,7 @@ static const struct pci_driver lpc_driver __pci_driver = {
#if IS_ENABLED(CONFIG_PIRQ_ROUTE)
void pirq_assign_irqs(const u8 * pirq)
{
- device_t lpc;
+ struct device *lpc;
lpc = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX900_LPC, 0);
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index 3f839c7f72..66b2def370 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -57,7 +57,7 @@ uint64_t get_uma_memory_base(void)
return uma_memory_base;
}
-static u64 vx900_get_top_of_ram(device_t mcu)
+static u64 vx900_get_top_of_ram(struct device *mcu)
{
u16 reg16;
/* The last valid DRAM address is computed by the MCU
@@ -94,7 +94,7 @@ static void killme_debug_4g_remap_reg(u32 reg32)
*
* @return The new top of memory.
*/
-static u64 vx900_remap_above_4g(device_t mcu, u32 tolm)
+static u64 vx900_remap_above_4g(struct device *mcu, u32 tolm)
{
size_t i;
u8 reg8, start8, end8, start, end;
@@ -214,7 +214,7 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm)
return newtor;
}
-static void vx900_set_resources(device_t dev)
+static void vx900_set_resources(struct device *dev)
{
u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk;
@@ -226,9 +226,9 @@ static void vx900_set_resources(device_t dev)
"========================================\n");
int idx = 10;
- const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VX900_MEMCTRL,
- 0);
+ struct device *const mcu = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_MEMCTRL,
+ 0);
if (!mcu) {
die("Something is terribly wrong.\n"
" We tried locating the MCU on the PCI bus, "
@@ -283,7 +283,7 @@ static void vx900_set_resources(device_t dev)
assign_resources(dev->link_list);
}
-static void vx900_read_resources(device_t dev)
+static void vx900_read_resources(struct device *dev)
{
/* Our fixed resources start at 0 */
int idx = 0;
@@ -310,7 +310,7 @@ static struct device_operations pci_domain_ops = {
.scan_bus = pci_domain_scan_bus,
};
-static void cpu_bus_init(device_t dev)
+static void cpu_bus_init(struct device *dev)
{
initialize_cpus(dev->link_list);
}
@@ -323,7 +323,7 @@ static struct device_operations cpu_bus_ops = {
.scan_bus = 0,
};
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c
index ae81739185..1d3ecd9938 100644
--- a/src/northbridge/via/vx900/pcie.c
+++ b/src/northbridge/via/vx900/pcie.c
@@ -35,7 +35,7 @@
* If the link never comes up, we hang.
*/
-static void vx900_pcie_link_init(device_t dev)
+static void vx900_pcie_link_init(struct device *dev)
{
u8 reg8;
u32 reg32;
@@ -81,12 +81,12 @@ static void vx900_pcie_link_init(device_t dev)
* time? */
}
-static void vx900_pex_dev_set_resources(device_t dev)
+static void vx900_pex_dev_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
-static void vx900_pex_init(device_t dev)
+static void vx900_pex_init(struct device *dev)
{
/* FIXME: For some reason, PEX0 hangs on init. Find issue, fix it. */
if ((dev->path.pci.devfn & 0x7) == 0)
diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c
index e0a54bdaee..4df0053874 100644
--- a/src/northbridge/via/vx900/sata.c
+++ b/src/northbridge/via/vx900/sata.c
@@ -71,7 +71,7 @@ static void vx900_print_sata_errors(u32 flags)
printk(BIOS_DEBUG, "\tUNRECOGNIZED FIS type\n");
}
-static void vx900_dbg_sata_errors(device_t dev)
+static void vx900_dbg_sata_errors(struct device *dev)
{
/* Port 0 */
if (pci_read_config8(dev, 0xa0) & (1 << 0)) {
@@ -100,7 +100,7 @@ static sata_phy_config reference_ephy = {
0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
-static u32 sata_phy_read32(device_t dev, u8 index)
+static u32 sata_phy_read32(struct device *dev, u8 index)
{
/* The SATA PHY control registers are accessed by a funny index/value
* scheme. Each byte (0,1,2,3) has its own 4-bit index */
@@ -112,7 +112,7 @@ static u32 sata_phy_read32(device_t dev, u8 index)
return pci_read_config32(dev, 0x64);
}
-static void sata_phy_write32(device_t dev, u8 index, u32 val)
+static void sata_phy_write32(struct device *dev, u8 index, u32 val)
{
/* The SATA PHY control registers are accessed by a funny index/value
* scheme. Each byte (0,1,2,3) has its own 4-bit index */
@@ -124,7 +124,7 @@ static void sata_phy_write32(device_t dev, u8 index, u32 val)
pci_write_config32(dev, 0x64, val);
}
-static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg)
+static void vx900_sata_read_phy_config(struct device *dev, sata_phy_config cfg)
{
size_t i;
u32 *data = (u32 *) cfg;
@@ -133,7 +133,7 @@ static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg)
}
}
-static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg)
+static void vx900_sata_write_phy_config(struct device *dev, sata_phy_config cfg)
{
size_t i;
u32 *data = (u32 *) cfg;
@@ -175,7 +175,7 @@ static void vx900_sata_dump_phy_config(sata_phy_config cfg)
* Our only option is to operate in IDE mode. We choose native IDE so that we
* can freely assign an IRQ, and are not forced to use IRQ14
*/
-static void vx900_native_ide_mode(device_t dev)
+static void vx900_native_ide_mode(struct device *dev)
{
/* Disable subclass write protect */
pci_mod_config8(dev, 0x45, 1 << 7, 0);
@@ -187,7 +187,7 @@ static void vx900_native_ide_mode(device_t dev)
pci_write_config8(dev, PCI_CLASS_PROG, 0x8f);
}
-static void vx900_sata_init(device_t dev)
+static void vx900_sata_init(struct device *dev)
{
/* Enable SATA primary channel IO access */
pci_mod_config8(dev, 0x40, 0, 1 << 1);
@@ -255,7 +255,7 @@ static void vx900_sata_init(device_t dev)
vx900_dbg_sata_errors(dev);
}
-static void vx900_sata_read_resources(device_t dev)
+static void vx900_sata_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
}
diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c
index 0fb55b3b05..8bdf25c828 100644
--- a/src/northbridge/via/vx900/traf_ctrl.c
+++ b/src/northbridge/via/vx900/traf_ctrl.c
@@ -45,10 +45,10 @@
* We are assuming this is called before the drivers/generic/ioapic code,
* which should be the case if devicetree.cb is set up properly.
*/
-static void vx900_north_ioapic_setup(device_t dev)
+static void vx900_north_ioapic_setup(struct device *dev)
{
u8 base_val;
- device_t ioapic;
+ struct device *ioapic;
ioapic_config_t *config;
/* Find the IOAPIC, and make sure it's set up correctly in devicetree.cb
* If it's not, then the generic ioapic driver will not set it up
@@ -103,7 +103,7 @@ static void vx900_north_ioapic_setup(device_t dev)
*
* FIXME: triple-quadruple-check this
*/
-static void vx900_pex_link_setup(device_t dev)
+static void vx900_pex_link_setup(struct device *dev)
{
u8 reg8;
struct northbridge_via_vx900_config *nb = (void *)dev->chip_info;
@@ -120,7 +120,7 @@ static void vx900_pex_link_setup(device_t dev)
pci_write_config8(dev, 0xb0, reg8);
}
-static void vx900_traf_ctr_init(device_t dev)
+static void vx900_traf_ctr_init(struct device *dev)
{
vx900_north_ioapic_setup(dev);
vx900_pex_link_setup(dev);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 05:04:51 +0000