4 files changed, 18 insertions, 21 deletions
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index bb5b2f7dd2..d4b93a6c6d 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -1661,10 +1661,10 @@ static int apply_cpu_errata_fixes(unsigned nodes)
 	unsigned node;
 	int needs_reset = 0;
 	for(node = 0; node < nodes; node++) {
+#if CONFIG_K8_REV_F_SUPPORT == 0
 		device_t dev;
 		uint32_t cmd;
 		dev = NODE_MC(node);
-#if CONFIG_K8_REV_F_SUPPORT == 0
 		if (is_cpu_pre_c0()) {
 
 			/* Errata 66
diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c
index 5c7ba00ff9..5928328f38 100644
--- a/src/northbridge/amd/amdk8/exit_from_self.c
+++ b/src/northbridge/amd/amdk8/exit_from_self.c
@@ -25,7 +25,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 	u32 pcidev;
 	u8 bitmask;
 	u8 is_post_rev_g;
-	u32 cpuid;
+	u32 local_cpuid;
 
 	for (i = 0; i < controllers; i++) {
 		if (!sysinfo->ctrl_present[i])
@@ -36,8 +36,8 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
 			continue;
 		}
 
-		cpuid = pci_read_config32(ctrl[i].f3, 0xfc);
-		is_post_rev_g = ((cpuid & 0xfff00) > 0x50f00);
+		local_cpuid = pci_read_config32(ctrl[i].f3, 0xfc);
+		is_post_rev_g = ((local_cpuid & 0xfff00) > 0x50f00);
 
 		/* ChipKill */
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 0ad5e4758a..3c96477cb3 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1859,7 +1859,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 		int latencies;
 		int latency;
 		int index;
-		int value;
+		int val;
 		u32 spd_device = ctrl->channel0[i];
 
 		if (!(meminfo->dimm_mask & (1 << i))) {
@@ -1893,14 +1893,14 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
 		}
 
 		/* Read the min_cycle_time for this latency */
-		value = spd_read_byte(spd_device, latency_indicies[index]);
-		if (value < 0) goto hw_error;
+		val = spd_read_byte(spd_device, latency_indicies[index]);
+		if (val < 0) goto hw_error;
 
-		value = convert_to_linear(value);
+		val = convert_to_linear(val);
 		/* All is good if the selected clock speed
 		 * is what I need or slower.
 		 */
-		if (value <= min_cycle_time) {
+		if (val <= min_cycle_time) {
 			continue;
 		}
 		/* Otherwise I have an error, disable the dimm */
@@ -2508,7 +2508,9 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
 {
 	uint32_t dword;
 	uint32_t dwordx;
+#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
 	unsigned SlowAccessMode = 0;
+#endif
 
 	long dimm_mask = meminfo->dimm_mask & 0x0f;
 
@@ -3007,8 +3009,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 	tsc_t tsc, tsc0[8];
 
 	printk_debug("sdram_enable: tsc0[8]: %p", &tsc0[0]);
-#endif
 	uint32_t dword;
+#endif
 
 	/* Error if I don't have memory */
 	if (memory_end_k(ctrl, controllers) == 0) {
@@ -3017,7 +3019,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 
 	/* Before enabling memory start the memory clocks */
 	for (i = 0; i < controllers; i++) {
-		uint32_t dtl, dch;
+		uint32_t dch;
 		if (!sysinfo->ctrl_present[ i ])
 			continue;
 		dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
@@ -3083,20 +3085,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 		}
 #endif
 
-#if 0
-		/* Set the DqsRcvEnTrain bit */
-		dword = pci_read_config32(ctrl[i].f2, DRAM_CTRL);
-		dword |= DC_DqsRcvEnTrain;
-		pci_write_config32(ctrl[i].f2, DRAM_CTRL, dword);
-#endif
-
 		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 		dcl |= DCL_InitDram;
 		pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
 	}
 
 	for (i = 0; i < controllers; i++) {
-		uint32_t dcl, dch, dcm;
+		uint32_t dcl, dcm;
 		if (!sysinfo->ctrl_present[ i ])
 			continue;
 		/* Skip everything if I don't have any memory on this controller */
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 2764e606be..d28e9422ef 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -522,7 +522,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
 	unsigned PatternA;
 	unsigned PatternB;
 
-	unsigned TestAddr0, TestAddr0B, TestAddr1, TestAddr1B = 0;
+	unsigned TestAddr0, TestAddr0B, TestAddr1 = 0, TestAddr1B = 0;
 
 	unsigned CurrRcvrCHADelay = 0;
 
@@ -530,7 +530,9 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
 
 	unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128;
 
+#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
 	unsigned cpu_f0_f1;
+#endif
 
 	if(Pass == DQS_FIRST_PASS) {
 		InitDQSPos4RcvrEn(ctrl);
@@ -2094,7 +2096,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr);
 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
 {
 	if(coreid) return; // only do it on core0
-	struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfox = (void*)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 	wait_till_sysinfo_in_ram(); // use pci to get it
 
 	if(sysinfox->mem_trained[nodeid] == 0x80) {