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-rw-r--r--src/northbridge/via/vx900/chrome9hd.c12
-rw-r--r--src/northbridge/via/vx900/early_host_bus_ctl.c16
-rw-r--r--src/northbridge/via/vx900/early_vx900.c4
-rw-r--r--src/northbridge/via/vx900/lpc.c20
-rw-r--r--src/northbridge/via/vx900/memmap.c2
-rw-r--r--src/northbridge/via/vx900/northbridge.c2
-rw-r--r--src/northbridge/via/vx900/pci_util.c42
-rw-r--r--src/northbridge/via/vx900/raminit_ddr3.c94
-rw-r--r--src/northbridge/via/vx900/sata.c16
-rw-r--r--src/northbridge/via/vx900/traf_ctrl.c2
-rw-r--r--src/northbridge/via/vx900/vx900.h12
11 files changed, 84 insertions, 138 deletions
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
index 8d2cf9c89f..abba4d3b34 100644
--- a/src/northbridge/via/vx900/chrome9hd.c
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -151,7 +151,7 @@ static void chrome9hd_handle_uma(struct device *dev)
pci_write_config8(dev, 0xb2, ((0xff << (fb_pow - 2)) & ~(1 << 7)));
vga_sr_write(0x68, (0xff << (fb_pow - 1)));
/* And also that the framebuffer is in the system, RAM */
- pci_mod_config8(dev, 0xb0, 0, 1 << 0);
+ pci_or_config8(dev, 0xb0, 1 << 0);
}
/**
@@ -175,13 +175,13 @@ static void chrome9hd_biosguide_init_seq(struct device *dev)
/* Step 1 - Enable VGA controller */
/* FIXME: This is the VGA hole @ 640k-768k, and the vga port io
* We need the port IO, but can we disable the memory hole? */
- pci_mod_config8(mcu, 0xa4, 0, (1 << 7)); /* VGA memory hole */
+ pci_or_config8(mcu, 0xa4, (1 << 7)); /* VGA memory hole */
/* Step 2 - Forward MDA cycles to GFX */
- pci_mod_config8(host, 0x4e, 0, (1 << 1));
+ pci_or_config8(host, 0x4e, (1 << 1));
/* Step 3 - Enable GFX I/O space */
- pci_mod_config8(dev, PCI_COMMAND, 0, PCI_COMMAND_IO);
+ pci_or_config8(dev, PCI_COMMAND, PCI_COMMAND_IO);
/* Step 4 - Enable video subsystem */
vga_enable_mask((1 << 0), (1 << 0));
@@ -248,7 +248,7 @@ static void chrome9hd_enable(struct device *dev)
struct device *mcu = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
/* FIXME: here? -=- ACLK 250MHz */
- pci_mod_config8(mcu, 0xbb, 0, 0x01);
+ pci_or_config8(mcu, 0xbb, 0x01);
}
static void chrome9hd_disable(struct device *dev)
@@ -257,7 +257,7 @@ static void chrome9hd_disable(struct device *dev)
PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
/* Disable GFX - This step effectively renders the GFX inert
* It won't even show up as a PCI device during enumeration */
- pci_mod_config8(mcu, 0xa1, 1 << 7, 0);
+ pci_update_config8(mcu, 0xa1, (u8)~(1 << 7), 0);
}
static struct device_operations chrome9hd_operations = {
diff --git a/src/northbridge/via/vx900/early_host_bus_ctl.c b/src/northbridge/via/vx900/early_host_bus_ctl.c
index 159b2a4273..92bb44dda0 100644
--- a/src/northbridge/via/vx900/early_host_bus_ctl.c
+++ b/src/northbridge/via/vx900/early_host_bus_ctl.c
@@ -19,32 +19,32 @@
static void vx900_cpu_bus_preram_setup(void)
{
/* Faster CPU to DRAM Cycle */
- pci_mod_config8(HOST_BUS, 0x50, 0x0f, 0x08);
+ pci_update_config8(HOST_BUS, 0x50, ~0x0f, 0x08);
/* CPU Interface Control - Basic Options */
- pci_mod_config8(HOST_BUS, 0x51, 0, 0x6c);
+ pci_or_config8(HOST_BUS, 0x51, 0x6c);
/*CPU Interface Control - Advanced Options */
pci_write_config8(HOST_BUS, 0x52, 0xc7);
/* Enable 8QW burst and 4QW request merging [4] and [2]
* and special mode for read cycles bit[3] */
- pci_mod_config8(HOST_BUS, 0x54, 0, (1 << 4) | (1 << 2) | (1 << 3));
+ pci_or_config8(HOST_BUS, 0x54, (1 << 4) | (1 << 2) | (1 << 3));
/* High priority upstream requests on V4 bus */
pci_write_config8(HOST_BUS, 0x56, 0x03);
/* CPU to DRAM extra 1T access control */
- pci_mod_config8(HOST_BUS, 0x59, 0x00, (1 << 2));
+ pci_or_config8(HOST_BUS, 0x59, (1 << 2));
/* Queue reordering */
- pci_mod_config8(HOST_BUS, 0x5f, 0x00, (1 << 6));
+ pci_or_config8(HOST_BUS, 0x5f, (1 << 6));
/* Only Write cycle of CPU->GFXCTL will flush the CPU->Memory FIFO */
- pci_mod_config8(HOST_BUS, 0x98, 0x00, 0x60);
+ pci_or_config8(HOST_BUS, 0x98, 0x60);
/* 1T delay for data on CPU bus */
pci_write_config8(HOST_BUS, 0x9e, 0x0e);
/* Arbitrate ownership of DRAM controller a few cycles earlier */
- pci_mod_config8(HOST_BUS, 0x9f, 0x00, (1 << 7));
+ pci_or_config8(HOST_BUS, 0x9f, (1 << 7));
/* Write retire policy */
pci_write_config8(HOST_BUS, 0x5d, 0xa2);
/* Occupancy timer */
pci_write_config8(HOST_BUS, 0x53, 0x44);
/* Medium Threshold for Write Retire Policy - 6 requests */
- pci_mod_config8(HOST_BUS, 0x56, 0x00, 0x60);
+ pci_or_config8(HOST_BUS, 0x56, 0x60);
/* Bandwidth timer */
pci_write_config8(HOST_BUS, 0x5e, 0x44);
}
diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c
index 126094101c..fe858b6800 100644
--- a/src/northbridge/via/vx900/early_vx900.c
+++ b/src/northbridge/via/vx900/early_vx900.c
@@ -109,7 +109,7 @@ void vx900_disable_legacy_rom_shadow(void)
pci_write_config8(MCU, 0x83, 0x31);
/* Bits 6:0 are the ROM shadow on top of 4G, so leave those untouched */
- pci_mod_config8(LPC, 0x41, 1 << 7, 0); /* LPC ROM 896k - 960k */
+ pci_update_config8(LPC, 0x41, (u8)~(1 << 7), 0); /* LPC ROM 896k - 960k */
pci_write_config8(SNMIC, 0x61, 0); /* 768k - 832k */
pci_write_config8(SNMIC, 0x62, 0); /* 832k - 896k */
@@ -126,5 +126,5 @@ void vx900_disable_legacy_rom_shadow(void)
void vx900_disable_gfx(void)
{
/* Disable GFX */
- pci_mod_config8(MCU, 0xa1, 1 << 7, 0);
+ pci_update_config8(MCU, 0xa1, (u8)~(1 << 7), 0);
}
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index 27e23846ee..40c4299d95 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -53,7 +53,7 @@ static void vx900_lpc_misc_stuff(struct device *dev)
struct northbridge_via_vx900_config *nb = (void *)dev->chip_info;
/* GPIO 11,10 to SATALED [1,0] */
- pci_mod_config8(dev, 0xe4, 0, 1 << 0);
+ pci_or_config8(dev, 0xe4, 1 << 0);
/* Route the external interrupt line */
extint = nb->ext_int_route_to_pirq;
@@ -65,7 +65,7 @@ static void vx900_lpc_misc_stuff(struct device *dev)
extint);
val = extint - 'A';
val |= (1 << 3); /* bit3 enables the external int */
- pci_mod_config8(dev, 0x55, 0xf, val);
+ pci_update_config8(dev, 0x55, ~0xf, val);
}
}
@@ -78,11 +78,11 @@ static void vx900_lpc_dma_setup(struct device *dev)
/* FIXME: Setting this seems to hang our system */
/* Positive decoding for ROM + APIC + On-board IO ports */
- pci_mod_config8(dev, 0x6c, 0, (1 << 2) | (1 << 3) | (1 << 7));
+ pci_or_config8(dev, 0x6c, (1 << 2) | (1 << 3) | (1 << 7));
/* Enable DMA channels. BIOS guide recommends DMA channel 2 off */
pci_write_config8(dev, 0x53, 0xfb);
/* Disable PCI/DMA Memory Cycles Output to PCI Bus */
- pci_mod_config8(dev, 0x5b, (1 << 5), 0);
+ pci_update_config8(dev, 0x5b, ~(1 << 5), 0);
/* DMA bandwidth control - Improved bandwidth */
pci_write_config8(dev, 0x53, 0xff);
/* ISA Positive Decoding control */
@@ -147,20 +147,20 @@ static void vx900_lpc_ioapic_setup(struct device *dev)
* So much work for one line of code. Talk about bloat :)
* The 8259 PIC should still work even if the IOAPIC is enabled, so
* there's no crime in enabling the IOAPIC here. */
- pci_mod_config8(dev, 0x58, 0, 1 << 6);
+ pci_or_config8(dev, 0x58, 1 << 6);
}
static void vx900_lpc_interrupt_stuff(struct device *dev)
{
/* Enable setting trigger mode through 0x4d0, and 0x4d1 ports
* And enable I/O recovery time */
- pci_mod_config8(dev, 0x40, 0, (1 << 2) | (1 << 6));
+ pci_or_config8(dev, 0x40, (1 << 2) | (1 << 6));
/* Set serial IRQ frame width to 6 PCI cycles (recommended by VIA)
* And enable serial IRQ */
- pci_mod_config8(dev, 0x52, 3 << 0, (1 << 3) | (1 << 0));
+ pci_update_config8(dev, 0x52, ~(3 << 0), (1 << 3) | (1 << 0));
/* Disable IRQ12 storm FIXME: bad comment */
- pci_mod_config8(dev, 0x51, (1 << 2), 0);
+ pci_update_config8(dev, 0x51, ~(1 << 2), 0);
pci_write_config8(dev, 0x4c, (1 << 6));
@@ -253,12 +253,12 @@ void pirq_assign_irqs(const u8 *pirq)
PCI_DEVICE_ID_VIA_VX900_LPC, 0);
/* Take care of INTA -> INTD */
- pci_mod_config8(lpc, 0x55, (0xf << 4), pirq[0] << 4);
+ pci_update_config8(lpc, 0x55, (u8)~(0xf << 4), pirq[0] << 4);
pci_write_config8(lpc, 0x56, pirq[1] | (pirq[2] << 4));
pci_write_config8(lpc, 0x57, pirq[3] << 4);
/* Enable INTE -> INTH to be on separate IRQs */
- pci_mod_config8(lpc, 0x46, 0, 1 << 4);
+ pci_or_config8(lpc, 0x46, 1 << 4);
/* Now do INTE -> INTH */
pci_write_config8(lpc, 0x44, pirq[4] | (pirq[5] << 4));
pci_write_config8(lpc, 0x45, pirq[6] | (pirq[7] << 4));
diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c
index 8cc7607356..9940502d27 100644
--- a/src/northbridge/via/vx900/memmap.c
+++ b/src/northbridge/via/vx900/memmap.c
@@ -83,7 +83,7 @@ void vx900_set_chrome9hd_fb_size(u32 size_mb)
fb_pow--;
size_mb = (1 << fb_pow);
- pci_mod_config8(MCU, 0xa1, 7 << 4, (fb_pow - 2) << 4);
+ pci_update_config8(MCU, 0xa1, ~(7 << 4), (fb_pow - 2) << 4);
}
/* Gets the configured framebuffer size as a power of 2 */
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index ca414506df..41a1073d89 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -129,7 +129,7 @@ static u64 vx900_remap_above_4g(struct device *mcu, u32 tolm)
/* The "start remapping from where ?" register */
reg16 = ((tolm >> 20) & 0xfff) << 4;
- pci_mod_config16(mcu, 0x84, 0xfff0, reg16);
+ pci_update_config16(mcu, 0x84, (u16)~0xfff0, reg16);
/* Find the chunk size */
tor = vx900_get_top_of_ram(mcu);
diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c
index 08e2b54c37..afd35a18e8 100644
--- a/src/northbridge/via/vx900/pci_util.c
+++ b/src/northbridge/via/vx900/pci_util.c
@@ -38,45 +38,3 @@ void dump_pci_device(struct device *dev)
printk(BIOS_DEBUG, "\n");
}
}
-
-#ifdef __SIMPLE_DEVICE__
-void pci_mod_config8(pci_devfn_t dev, unsigned int where, uint8_t clr_mask,
- uint8_t set_mask)
-#else
-void pci_mod_config8(struct device *dev, unsigned int where, uint8_t clr_mask,
- uint8_t set_mask)
-#endif
-{
- uint8_t reg8 = pci_read_config8(dev, where);
- reg8 &= ~clr_mask;
- reg8 |= set_mask;
- pci_write_config8(dev, where, reg8);
-}
-
-#ifdef __SIMPLE_DEVICE__
-void pci_mod_config16(pci_devfn_t dev, unsigned int where,
- uint16_t clr_mask, uint16_t set_mask)
-#else
-void pci_mod_config16(struct device *dev, unsigned int where,
- uint16_t clr_mask, uint16_t set_mask)
-#endif
-{
- uint16_t reg16 = pci_read_config16(dev, where);
- reg16 &= ~clr_mask;
- reg16 |= set_mask;
- pci_write_config16(dev, where, reg16);
-}
-
-#ifdef __SIMPLE_DEVICE__
-void pci_mod_config32(pci_devfn_t dev, unsigned int where,
- uint32_t clr_mask, uint32_t set_mask)
-#else
-void pci_mod_config32(struct device *dev, unsigned int where,
- uint32_t clr_mask, uint32_t set_mask)
-#endif
-{
- uint32_t reg32 = pci_read_config32(dev, where);
- reg32 &= ~clr_mask;
- reg32 |= set_mask;
- pci_write_config32(dev, where, reg32);
-}
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index 7acab31247..59d206c28c 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -485,9 +485,9 @@ static void vx900_dram_driving_ctrl(const dimm_info * dimm)
/* Enable strong CLK driving for DIMMs with more than one rank */
if (dimm->dimm[0].ranks > 1)
- pci_mod_config8(MCU, 0xd6, 0, (1 << 7));
+ pci_or_config8(MCU, 0xd6, (1 << 7));
if (dimm->dimm[1].ranks > 1)
- pci_mod_config8(MCU, 0xd6, 0, (1 << 6));
+ pci_or_config8(MCU, 0xd6, (1 << 6));
/* DRAM ODT Lookup Table */
for (i = 0;; i++) {
@@ -528,7 +528,7 @@ static void vx900_map_pr_vr(u8 pr, u8 vr)
val = 0x8 | vr;
/* Now move the value to the appropriate PR */
val <<= (pr * 4);
- pci_mod_config16(MCU, 0x54, 0xf << (pr * 4), val);
+ pci_update_config16(MCU, 0x54, ~(0xf << (pr * 4)), val);
printram("Mapping PR %u to VR %u\n", pr, vr);
}
@@ -629,7 +629,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl)
val = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
printram("Selected tWTR : %uT\n", val);
reg8 |= ((val - 2) & 0x7);
- pci_mod_config8(MCU, 0xc4, 0x3f, reg8);
+ pci_update_config8(MCU, 0xc4, ~0x3f, reg8);
/* DRAM Timing for All Ranks - VI
* [7:6] CKE Assertion Minimum Pulse Width
@@ -662,7 +662,7 @@ static void vx900_dram_freq(ramctr_timing * ctrl)
u8 val;
/* Step 1 - Reset the PLL */
- pci_mod_config8(MCU, 0x90, 0x00, 0x0f);
+ pci_or_config8(MCU, 0x90, 0x0f);
/* Wait at least 10 ns; VIA code delays by 640us */
udelay(640);
@@ -681,30 +681,30 @@ static void vx900_dram_freq(ramctr_timing * ctrl)
ctrl->tCK = TCK_266MHZ;
}
/* Restart the PLL with the desired frequency */
- pci_mod_config8(MCU, 0x90, 0x0f, val);
+ pci_update_config8(MCU, 0x90, ~0x0f, val);
/* Step 3 - Wait for PLL to stabilize */
udelay(2000);
/* Step 4 - Reset the DLL - Clear [7,4] */
- pci_mod_config8(MCU, 0x6b, 0x90, 0x00);
+ pci_update_config8(MCU, 0x6b, (u8)~0x90, 0x00);
udelay(2000);
/* Step 5 - Enable the DLL - Set bits [7,4] to 01b */
- pci_mod_config8(MCU, 0x6b, 0x00, 0x10);
+ pci_or_config8(MCU, 0x6b, 0x10);
udelay(2000);
/* Step 6 - Start DLL Calibration - Set bit [7] */
- pci_mod_config8(MCU, 0x6b, 0x00, 0x80);
+ pci_or_config8(MCU, 0x6b, 0x80);
udelay(5);
/* Step 7 - Finish DLL Calibration - Clear bit [7] */
- pci_mod_config8(MCU, 0x6b, 0x80, 0x00);
+ pci_update_config8(MCU, 0x6b, (u8)~0x80, 0x00);
/* Step 8 - If we have registered DIMMs, we need to set bit[0] */
if (spd_dimm_is_registered_ddr3(ctrl->dimm_type)) {
printram("Enabling RDIMM support in memory controller\n");
- pci_mod_config8(MCU, 0x6c, 0x00, 0x01);
+ pci_or_config8(MCU, 0x6c, 0x01);
}
}
@@ -803,7 +803,7 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom,
/* Was already done for us before calling us */
/* Step 08 - Set Fun3_RX6B[2:0] to 011b (MSR Enable). */
- pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */
+ pci_update_config8(MCU, 0x6b, ~0x07, 0x03); /* MSR Enable */
/* Step 09 - Issue MR2 cycle. Read a double word from the address
* depended on DRAM's Rtt_WR and CWL settings. */
@@ -853,7 +853,7 @@ static void vx900_dram_ddr3_do_sw_mrs(u8 ma_swap, enum ddr3_mr1_rtt_nom rtt_nom,
udelay(1000);
/* Step 13 - Set Fun3_RX6B[2:0] to 110b (Long ZQ calibration cmd) */
- pci_mod_config8(MCU, 0x6b, 0x07, 0x06); /* Long ZQ */
+ pci_update_config8(MCU, 0x6b, ~0x07, 0x06); /* Long ZQ */
/* Step 14 - Read a double word from any address of the DIMM. */
volatile_read(0);
udelay(1000);
@@ -873,9 +873,9 @@ static void vx900_dram_ddr3_dimm_init(const ramctr_timing * ctrl,
vx900_dram_set_ma_pin_map(VX900_MRS_MA_MAP);
/* Step 01 - Set Fun3_Rx6E[5] to 1b to support burst length. */
- pci_mod_config8(MCU, 0x6e, 0, 1 << 5);
+ pci_or_config8(MCU, 0x6e, 1 << 5);
/* Step 02 - Set Fun3_RX69[0] to 0b (Disable Multiple Page Mode). */
- pci_mod_config8(MCU, 0x69, (1 << 0), 0x00);
+ pci_update_config8(MCU, 0x69, ~(1 << 0), 0x00);
/* And set [7:6] to 10b ? */
pci_write_config8(MCU, 0x69, 0x87);
@@ -887,7 +887,7 @@ static void vx900_dram_ddr3_dimm_init(const ramctr_timing * ctrl,
pci_write_config8(MCU, 0x50, 0xd8);
/* Step 05 - Set Fun3_RX6B[5] to 1b to de-assert RESET# and wait for at
* least 500 us. */
- pci_mod_config8(MCU, 0x6b, 0x00, (1 << 5));
+ pci_or_config8(MCU, 0x6b, (1 << 5));
udelay(500);
/* Step 6 -> 15 - Set the target physical rank to virtual rank 0 and
@@ -903,9 +903,9 @@ static void vx900_dram_ddr3_dimm_init(const ramctr_timing * ctrl,
vx900_map_pr_vr(i, 0);
/* FIXME: Is this needed on HW init? */
- pci_mod_config8(MCU, 0x6b, 0x07, 0x01); /* Enable NOP */
+ pci_update_config8(MCU, 0x6b, ~0x07, 0x01); /* Enable NOP */
volatile_read(0x0); /* Do NOP */
- pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */
+ pci_update_config8(MCU, 0x6b, ~0x07, 0x03); /* MSR Enable */
/* See init_dram_by_rank.c and get_basic_information.c
* in the VIA provided code */
@@ -934,20 +934,20 @@ static void vx900_dram_ddr3_dimm_init(const ramctr_timing * ctrl,
0, 0);
/* Normal SDRAM Mode */
- pci_mod_config8(MCU, 0x6b, 0x07, 0x00);
+ pci_update_config8(MCU, 0x6b, ~0x07, 0x00);
/* Step 15, set the rank to virtual rank 3 */
vx900_map_pr_vr(i, 3);
}
/* Step 16 - Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */
- pci_mod_config8(MCU, 0x6b, 0x07, 0x00);
+ pci_update_config8(MCU, 0x6b, ~0x07, 0x00);
/* Set BA[0/1/2] to [A13/14/15] */
vx900_dram_set_ma_pin_map(VX900_CALIB_MA_MAP);
/* Step 17 - Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */
- pci_mod_config8(MCU, 0x69, 0x00, (1 << 0));
+ pci_or_config8(MCU, 0x69, (1 << 0));
printram("DIMM initialization sequence complete\n");
}
@@ -961,7 +961,7 @@ static void vx900_dram_send_soft_mrs(mrs_cmd_t cmd, u8 pin_swap)
{
u32 addr;
/* Set Fun3_RX6B[2:0] to 011b (MSR Enable). */
- pci_mod_config8(MCU, 0x6b, 0x07, (3 << 0));
+ pci_update_config8(MCU, 0x6b, ~0x07, (3 << 0));
/* Is this a funky rank with Address pins swapped? */
if (pin_swap)
cmd = ddr3_mrs_mirror_pins(cmd);
@@ -970,18 +970,18 @@ static void vx900_dram_send_soft_mrs(mrs_cmd_t cmd, u8 pin_swap)
/* Execute the MRS */
volatile_read(addr);
/* Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */
- pci_mod_config8(MCU, 0x6b, 0x07, 0x00);
+ pci_update_config8(MCU, 0x6b, ~0x07, 0x00);
}
static void vx900_dram_enter_read_leveling(u8 pinswap)
{
/* Precharge all before issuing read leveling MRS to DRAM */
- pci_mod_config8(MCU, 0x06b, 0x07, 0x02);
+ pci_update_config8(MCU, 0x06b, ~0x07, 0x02);
volatile_read(0x0);
udelay(1000);
/* Enable read leveling: Set D0F3Rx71[7]=1 */
- pci_mod_config8(MCU, 0x71, 0, (1 << 7));
+ pci_or_config8(MCU, 0x71, (1 << 7));
/* Put DRAM in read leveling mode */
mrs_cmd_t cmd = ddr3_get_mr3(1);
@@ -995,7 +995,7 @@ static void vx900_dram_exit_read_leveling(u8 pinswap)
vx900_dram_send_soft_mrs(cmd, pinswap);
/* Disable read leveling: Set D0F3Rx71[7]=0 */
- pci_mod_config8(MCU, 0x71, (1 << 7), 0);
+ pci_update_config8(MCU, 0x71, (u8)~(1 << 7), 0);
}
/*
@@ -1096,7 +1096,7 @@ static void vx900_rx_capture_range_calib(u8 pinswap)
const u32 cal_addr = 0x20;
/* Set IO calibration address */
- pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0));
+ pci_update_config16(MCU, 0x8c, (u16)~0xfff0, cal_addr & (0xfff0));
/* Data pattern must be 0x00 for this calibration
* See paragraph describing Rx8e */
pci_write_config8(MCU, 0x8e, 0x00);
@@ -1128,7 +1128,7 @@ static void vx900_rx_dqs_delay_calib(u8 pinswap)
const u8 ref_cnt = pci_read_config8(MCU, 0xc7);
pci_write_config8(MCU, 0xc7, 0);
/* Set IO calibration address */
- pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0));
+ pci_update_config16(MCU, 0x8c, (u16)~0xfff0, cal_addr & (0xfff0));
/* Data pattern must be 0x00 for this calibration
* See paragraph describing Rx8e */
pci_write_config8(MCU, 0x8e, 0x00);
@@ -1138,10 +1138,10 @@ static void vx900_rx_dqs_delay_calib(u8 pinswap)
/* From VIA code; Undocumented
* In theory this enables MODT[3:0] to be asserted */
- pci_mod_config8(MCU, 0x9e, 0, 0x80);
+ pci_or_config8(MCU, 0x9e, 0x80);
/* Trigger calibration: Set D0F3Rx71[1:0]=10b */
- pci_mod_config8(MCU, 0x71, 0x03, 0x02);
+ pci_update_config8(MCU, 0x71, ~0x03, 0x02);
/* Wait for calibration to complete */
while (pci_read_config8(MCU, 0x71) & 0x02);
@@ -1159,7 +1159,7 @@ static void vx900_tx_dqs_trigger_calib(u8 pattern)
/* Data pattern for calibration */
pci_write_config8(MCU, 0x8e, pattern);
/* Trigger calibration */
- pci_mod_config8(MCU, 0x75, 0, 0x20);
+ pci_or_config8(MCU, 0x75, 0x20);
/* Wait for calibration */
while (pci_read_config8(MCU, 0x75) & 0x20);
}
@@ -1171,9 +1171,9 @@ static void vx900_tx_dqs_delay_calib(void)
{
const u32 cal_addr = 0x00;
/* Set IO calibration address */
- pci_mod_config16(MCU, 0x8c, 0xfff0, cal_addr & (0xfff0));
+ pci_update_config16(MCU, 0x8c, (u16)~0xfff0, cal_addr & (0xfff0));
/* Set circuit to use calibration results - Clear Rx75[0] */
- pci_mod_config8(MCU, 0x75, 0x01, 0);
+ pci_update_config8(MCU, 0x75, ~0x01, 0);
/* Run calibration with first data pattern */
vx900_tx_dqs_trigger_calib(0x5a);
/* Run again with different pattern */
@@ -1188,7 +1188,7 @@ static void vx900_tx_dq_delay_calib(void)
/* Data pattern for calibration */
pci_write_config8(MCU, 0x8e, 0x5a);
/* Trigger calibration */
- pci_mod_config8(MCU, 0x75, 0, 0x02);
+ pci_or_config8(MCU, 0x75, 0x02);
/* Wait for calibration */
while (pci_read_config8(MCU, 0x75) & 0x02);
}
@@ -1217,7 +1217,7 @@ static void vx900_rxdqs_adjust(delay_range * dly)
}
/* Put Rx DQS delay into manual mode (Set Rx[2,0] to 01) */
- pci_mod_config8(MCU, 0x71, 0x05, 0x01);
+ pci_update_config8(MCU, 0x71, ~0x05, 0x01);
/* Now write the new settings */
vx900_delay_calib_mode_select(CALIB_RxDQS, CALIB_MANUAL);
vx900_write_0x78_0x7f(dly->avg);
@@ -1261,7 +1261,7 @@ static void vx900_dram_calibrate_receive_delays(vx900_delay_calib * delays,
dump_delay(rx_dq_cr->avg);
}
/* We need to put the setting on manual mode */
- pci_mod_config8(MCU, 0x71, 0, 1 << 4);
+ pci_or_config8(MCU, 0x71, 1 << 4);
vx900_delay_calib_mode_select(CALIB_RxDQ_CR, CALIB_MANUAL);
vx900_write_0x78_0x7f(rx_dq_cr->avg);
@@ -1276,7 +1276,7 @@ static void vx900_dram_calibrate_receive_delays(vx900_delay_calib * delays,
/* We're good to go. Switch to manual and write the manual
* setting */
- pci_mod_config8(MCU, 0x71, 0, 1 << 0);
+ pci_or_config8(MCU, 0x71, 1 << 0);
vx900_delay_calib_mode_select(CALIB_RxDQS, CALIB_MANUAL);
vx900_write_0x78_0x7f(rx_dqs->avg);
break;
@@ -1316,7 +1316,7 @@ static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq,
/************* TxDQ *************/
/* FIXME: not sure if multiple page mode should be enabled here
* Vendor BIOS does it */
- pci_mod_config8(MCU, 0x69, 0, 0x01);
+ pci_or_config8(MCU, 0x69, 0x01);
dq_tries++;
vx900_tx_dq_delay_calib();
@@ -1375,10 +1375,10 @@ static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl,
else
val = 0;
val++; /* FIXME: vendor BIOS sets this to 3 */
- pci_mod_config8(MCU, 0x74, (0x03 << 1), ((val & 0x03) << 1));
+ pci_update_config8(MCU, 0x74, ~(0x03 << 1), ((val & 0x03) << 1));
/* FIXME: The vendor BIOS increases the MD input delay - WHY ? */
- pci_mod_config8(MCU, 0xef, (3 << 4), 3 << 4);
+ pci_update_config8(MCU, 0xef, ~(3 << 4), 3 << 4);
/**** Write delay control ****/
/* FIXME: The vendor BIOS does this, but WHY?
@@ -1386,14 +1386,14 @@ static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl,
* to depend on the DRAM frequency.
*/
/* Early DQ/DQS for write cycles */
- pci_mod_config8(MCU, 0x76, (3 << 2), 2 << 2);
+ pci_update_config8(MCU, 0x76, ~(3 << 2), 2 << 2);
/* FIXME: The vendor BIOS does this - Output preamble ? */
pci_write_config8(MCU, 0x77, 0x10);
/* Set BA[0/1/2] to [A17/18/19] */
vx900_dram_set_ma_pin_map(VX900_MRS_MA_MAP);
/* Disable Multiple Page Mode - Set Rx69[0] to 0 */
- pci_mod_config8(MCU, 0x69, (1 << 0), 0x00);
+ pci_update_config8(MCU, 0x69, ~(1 << 0), 0x00);
/* It's very important that we keep all ranks which are not calibrated
* mapped to VR3. Even if we disable them, if they are mapped to VR0
@@ -1422,7 +1422,7 @@ static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl,
dump_delay_range(delay_cal.rx_dqs);
/* Enable multiple page mode for when calibrating transmit delays */
- pci_mod_config8(MCU, 0x69, 0, 1 << 1);
+ pci_or_config8(MCU, 0x69, 1 << 1);
/*
* Unlike the receive delays, we need to run the transmit calibration
@@ -1464,7 +1464,7 @@ static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl,
dump_delay(delay_cal.tx_dq[0].avg);
}
/* Write manual settings */
- pci_mod_config8(MCU, 0x75, 0, 0x01);
+ pci_or_config8(MCU, 0x75, 0x01);
vx900_delay_calib_mode_select(CALIB_TxDQS, CALIB_MANUAL);
vx900_write_0x78_0x7f(delay_cal.tx_dqs[0].avg);
vx900_delay_calib_mode_select(CALIB_TxDQ, CALIB_MANUAL);
@@ -1538,7 +1538,7 @@ static void vx900_dram_range(ramctr_timing * ctrl, rank_layout * ranks)
* all devices and know pci_tolm. */
tolm_mb = MIN(ramsize_mb, TOLM_3_5G >> 20);
u16 reg_tolm = (tolm_mb << 4) & 0xfff0;
- pci_mod_config16(MCU, 0x84, 0xfff0, reg_tolm);
+ pci_update_config16(MCU, 0x84, (u16)~0xfff0, reg_tolm);
printram("Initialized %u virtual ranks, with a total size of %u MB\n",
(int)vrank, ramsize_mb);
@@ -1609,10 +1609,10 @@ static void vx900_dram_write_final_config(ramctr_timing * ctrl)
/* FIXME: Why are we doing this? */
/* Tri-state MCSi# when rank is in self-refresh */
- pci_mod_config8(MCU, 0x99, 0, 0x0f);
+ pci_or_config8(MCU, 0x99, 0x0f);
/* Enable paging mode and 8 page registers */
- pci_mod_config8(MCU, 0x69, 0, 0xe5);
+ pci_or_config8(MCU, 0x69, 0xe5);
/* Enable automatic triggering of short ZQ calibration */
pci_write_config8(MCU, 0xc8, 0x80);
diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c
index 4df0053874..d6f4c836c0 100644
--- a/src/northbridge/via/vx900/sata.c
+++ b/src/northbridge/via/vx900/sata.c
@@ -178,11 +178,11 @@ static void vx900_sata_dump_phy_config(sata_phy_config cfg)
static void vx900_native_ide_mode(struct device *dev)
{
/* Disable subclass write protect */
- pci_mod_config8(dev, 0x45, 1 << 7, 0);
+ pci_update_config8(dev, 0x45, (u8)~(1 << 7), 0);
/* Change the device class to IDE */
pci_write_config16(dev, PCI_CLASS_DEVICE, PCI_CLASS_STORAGE_IDE);
/* Re-enable subclass write protect */
- pci_mod_config8(dev, 0x45, 0, 1 << 7);
+ pci_or_config8(dev, 0x45, 1 << 7);
/* Put it in native IDE mode */
pci_write_config8(dev, PCI_CLASS_PROG, 0x8f);
}
@@ -190,20 +190,20 @@ static void vx900_native_ide_mode(struct device *dev)
static void vx900_sata_init(struct device *dev)
{
/* Enable SATA primary channel IO access */
- pci_mod_config8(dev, 0x40, 0, 1 << 1);
+ pci_or_config8(dev, 0x40, 1 << 1);
/* Just SATA, so it makes sense to be in native SATA mode */
vx900_native_ide_mode(dev);
/* TP Layer Idle at least 20us before the Following Command */
- pci_mod_config8(dev, 0x53, 0, 1 << 7);
+ pci_or_config8(dev, 0x53, 1 << 7);
/* Resend COMRESET When Recovering SATA Gen2 Device Error */
- pci_mod_config8(dev, 0x62, 1 << 1, 1 << 7);
+ pci_update_config8(dev, 0x62, ~(1 << 1), 1 << 7);
/* Fix "PMP Device Can't Detect HDD Normally" (VIA Porting Guide)
* SATA device detection will not work unless we clear these bits.
* Without doing this, SeaBIOS (and potentially other payloads) will
* timeout when detecting SATA devices */
- pci_mod_config8(dev, 0x89, (1 << 3) | (1 << 6), 0);
+ pci_update_config8(dev, 0x89, ~(1 << 3) | (1 << 6), 0);
/* 12.7 Two Software Resets May Affect the System
* When the software does the second reset before the first reset
@@ -216,7 +216,7 @@ static void vx900_sata_init(struct device *dev)
* second one anymore. The BSY bit of slave port would be always 1 after
* the second software reset issues. BIOS should set the following
* bit to avoid this issue. */
- pci_mod_config8(dev, 0x80, 0, 1 << 6);
+ pci_or_config8(dev, 0x80, 1 << 6);
/* We need to set the EPHY values before doing anything with the link */
sata_phy_config ephy;
@@ -243,7 +243,7 @@ static void vx900_sata_init(struct device *dev)
pci_write_config32(dev, 0xac, 0xffffffff);
/* Start OOB link negotiation sequence */
- pci_mod_config8(dev, 0xb9, 0, 3 << 4);
+ pci_or_config8(dev, 0xb9, 3 << 4);
/* FIXME: From now on, we are just doing DEBUG stuff
* Wait until PHY communication is enabled */
diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c
index c2b4a48052..734defcf25 100644
--- a/src/northbridge/via/vx900/traf_ctrl.c
+++ b/src/northbridge/via/vx900/traf_ctrl.c
@@ -93,7 +93,7 @@ static void vx900_north_ioapic_setup(struct device *dev)
/* Second register of the base.
* Bit[7] also enables the IOAPIC and bit[5] enables MSI cycles */
base_val = (((uintptr_t)config->base) >> 16) & 0xf;
- pci_mod_config8(dev, 0x40, 0, base_val | (1 << 7) | (1 << 5));
+ pci_or_config8(dev, 0x40, base_val | (1 << 7) | (1 << 5));
}
/*
diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h
index a2a360ac0d..29fc472b3d 100644
--- a/src/northbridge/via/vx900/vx900.h
+++ b/src/northbridge/via/vx900/vx900.h
@@ -43,20 +43,8 @@ uint64_t get_uma_memory_base(void);
#ifdef __SIMPLE_DEVICE__
void dump_pci_device(pci_devfn_t dev);
-void pci_mod_config8(pci_devfn_t dev, unsigned int where,
- uint8_t clr_mask, uint8_t set_mask);
-void pci_mod_config16(pci_devfn_t dev, unsigned int where,
- uint16_t clr_mask, uint16_t set_mask);
-void pci_mod_config32(pci_devfn_t dev, unsigned int where,
- uint32_t clr_mask, uint32_t set_mask);
#else
void dump_pci_device(struct device *dev);
-void pci_mod_config8(struct device *dev, unsigned int where,
- uint8_t clr_mask, uint8_t set_mask);
-void pci_mod_config16(struct device *dev, unsigned int where,
- uint16_t clr_mask, uint16_t set_mask);
-void pci_mod_config32(struct device *dev, unsigned int where,
- uint32_t clr_mask, uint32_t set_mask);
#endif
#endif /* __VX900_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 00:36:31 +0000