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-rw-r--r--src/northbridge/intel/i945/northbridge.c39
1 files changed, 20 insertions, 19 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 0e8ea7e77e..20c911620c 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h>
+#include <commonlib/helpers.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <stdint.h>
@@ -11,32 +12,33 @@
#include <cpu/intel/smm_reloc.h>
#include "i945.h"
-static int get_pcie_bar(u32 *base)
+static int decode_pcie_bar(u32 *const base, u32 *const len)
{
- struct device *dev;
- u32 pciexbar_reg;
-
*base = 0;
+ *len = 0;
- dev = pcidev_on_root(0, 0);
+ struct device *dev = pcidev_on_root(0, 0);
if (!dev)
return 0;
- pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+ const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0)))
return 0;
switch ((pciexbar_reg >> 1) & 3) {
- case 0: // 256MB
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
- return 256;
- case 1: // 128M
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
- return 128;
- case 2: // 64M
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
- return 64;
+ case 0: /* 256MB */
+ *base = pciexbar_reg & (0x0f << 28);
+ *len = 256 * MiB;
+ return 1;
+ case 1: /* 128M */
+ *base = pciexbar_reg & (0x1f << 27);
+ *len = 128 * MiB;
+ return 1;
+ case 2: /* 64M */
+ *base = pciexbar_reg & (0x3f << 26);
+ *len = 64 * MiB;
+ return 1;
}
return 0;
@@ -162,13 +164,12 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(struct device *dev)
{
- u32 pcie_config_base;
- int buses;
+ u32 pcie_config_base, pcie_config_len;
pci_dev_read_resources(dev);
- buses = get_pcie_bar(&pcie_config_base);
- if (buses) {
+ if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) {
+ const int buses = pcie_config_len / MiB;
struct resource *resource = new_resource(dev, PCIEXBAR);
mmconf_resource_init(resource, pcie_config_base, buses);
}