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-rw-r--r--src/northbridge/amd/agesa/oem_s3.c15
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/s3utils.c13
-rw-r--r--src/northbridge/intel/common/mrc_cache.c8
3 files changed, 17 insertions, 19 deletions
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
index e3d58c21d0..02c384ac8b 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -96,20 +96,19 @@ AGESA_STATUS OemS3LateRestore(AMD_S3_PARAMS *dataBlock)
static int spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len)
{
#if IS_ENABLED(CONFIG_SPI_FLASH)
- struct spi_flash *flash;
+ struct spi_flash flash;
spi_init();
- flash = spi_flash_probe(0, 0);
- if (!flash)
+ if (spi_flash_probe(0, 0, &flash))
return -1;
- spi_flash_volatile_group_begin(flash);
+ spi_flash_volatile_group_begin(&flash);
- spi_flash_erase(flash, pos, size);
- spi_flash_write(flash, pos, sizeof(len), &len);
- spi_flash_write(flash, pos + sizeof(len), len, buf);
+ spi_flash_erase(&flash, pos, size);
+ spi_flash_write(&flash, pos, sizeof(len), &len);
+ spi_flash_write(&flash, pos + sizeof(len), len, buf);
- spi_flash_volatile_group_end(flash);
+ spi_flash_volatile_group_end(&flash);
return 0;
#else
return -1;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index f69b6c4496..4100b2637d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -1100,7 +1100,7 @@ int8_t save_mct_information_to_nvram(void)
printk(BIOS_DEBUG, "Writing AMD DCT configuration to Flash\n");
- struct spi_flash *flash;
+ struct spi_flash flash;
ssize_t s3nv_offset;
struct amd_s3_persistent_data *persistent_data;
@@ -1140,23 +1140,22 @@ int8_t save_mct_information_to_nvram(void)
/* Initialize SPI and detect devices */
spi_init();
- flash = spi_flash_probe(0, 0);
- if (!flash) {
+ if (spi_flash_probe(0, 0, &flash)) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return -1;
}
- spi_flash_volatile_group_begin(flash);
+ spi_flash_volatile_group_begin(&flash);
/* Erase and write data structure */
- spi_flash_erase(flash, s3nv_offset, CONFIG_S3_DATA_SIZE);
- spi_flash_write(flash, s3nv_offset,
+ spi_flash_erase(&flash, s3nv_offset, CONFIG_S3_DATA_SIZE);
+ spi_flash_write(&flash, s3nv_offset,
sizeof(struct amd_s3_persistent_data), persistent_data);
/* Deallocate temporary data structures */
free(persistent_data);
- spi_flash_volatile_group_end(flash);
+ spi_flash_volatile_group_end(&flash);
/* Allow training bypass if DIMM configuration is unchanged on next boot */
nvram = 1;
diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c
index a15812311b..2fc8d96ee5 100644
--- a/src/northbridge/intel/common/mrc_cache.c
+++ b/src/northbridge/intel/common/mrc_cache.c
@@ -160,6 +160,7 @@ static void update_mrc_cache(void *unused)
struct mrc_data_container *cache, *cache_base;
u32 cache_size;
int ret;
+ struct spi_flash flash;
if (!current) {
printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n");
@@ -192,8 +193,7 @@ static void update_mrc_cache(void *unused)
// 1. use spi_flash_probe() to find the flash, then
spi_init();
- struct spi_flash *flash = spi_flash_probe(0, 0);
- if (!flash) {
+ if (spi_flash_probe(0, 0, &flash)) {
printk(BIOS_DEBUG, "Could not find SPI device\n");
return;
}
@@ -212,7 +212,7 @@ static void update_mrc_cache(void *unused)
"Need to erase the MRC cache region of %d bytes at %p\n",
cache_size, cache_base);
- spi_flash_erase(flash, to_flash_offset(flash, cache_base),
+ spi_flash_erase(&flash, to_flash_offset(&flash, cache_base),
cache_size);
/* we will start at the beginning again */
@@ -221,7 +221,7 @@ static void update_mrc_cache(void *unused)
// 4. write mrc data with flash->write()
printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n",
cache);
- ret = spi_flash_write(flash, to_flash_offset(flash, cache),
+ ret = spi_flash_write(&flash, to_flash_offset(&flash, cache),
current->mrc_data_size + sizeof(*current), current);
if (ret)