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-rw-r--r--src/northbridge/intel/sch/sch.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h
index 4f49beb041..5700842e90 100644
--- a/src/northbridge/intel/sch/sch.h
+++ b/src/northbridge/intel/sch/sch.h
@@ -38,7 +38,7 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
#define DEFAULT_RCBABASE 0xfed1c000
-#define DEFAULT_PCIEXBAR 0xe0000000 /* 4 KB per PCIe device */
+#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
/* IGD */
#define GGC 0x52