15 files changed, 59 insertions, 22 deletions

diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 472e55594f..80b956ac07 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1179,6 +1179,14 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32
 		offset_pci_dev, u32 offset_io_base);
 
 void setup_resource_map_x(const u32 *register_values, u32 max);
+
+/* reset_test.c */
+u32 cpu_init_detected(u8 nodeid);
+u32 bios_reset_detected(void);
+u32 cold_reset_detected(void);
+u32 other_reset_detected(void);
+u32 get_sblk(void);
+u8 get_sbbusn(u8 sblk);
 #endif
 
 #endif /* AMDFAM10_H */
diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c
index 4ce3e9a471..adfff0f6e3 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_conf.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c
@@ -61,6 +61,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
 	return d;
 }
 
+#if CONFIG_AMDMCT == 0
 static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
 {
 	u32 i;
@@ -117,8 +118,9 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
 	pci_write_config32(dev, 0x124, d.mask>>8);
 
 }
+#endif
 
-
+#if CONFIG_AMDMCT == 0
 static void set_DctSelBaseAddr(u32 i, u32 sel_m)
 {
 	device_t dev;
@@ -152,7 +154,6 @@ static u32 get_DctSelBaseAddr(u32 i)
 	return sel_m;
 }
 
-#if CONFIG_AMDMCT == 0
 #ifdef UNUSED_CODE
 static void set_DctSelHiEn(u32 i, u32 val)
 {
@@ -234,6 +235,7 @@ static u32 get_one_DCT(struct mem_info *meminfo)
 
 	return one_DCT;
 }
+
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 // See that other copy in northbridge.c
 static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
@@ -574,7 +576,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
 }
 #endif
 
-
+#ifdef UNUSED_CODE
 static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
 					sys_info_conf_t *sysinfo)
 {
@@ -616,7 +618,7 @@ static void re_set_all_config_map_reg(u32 nodes, u32 segbit,
 	}
 
 }
-
+#endif
 
 static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo)
 {
@@ -660,7 +662,7 @@ static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index,
 
 }
 
-
+#ifdef UNUSED_CODE
 static  void set_BusSegmentEn(u32 node, u32 segbit)
 {
 #if CONFIG_PCI_BUS_SEGN_BITS
@@ -679,6 +681,7 @@ static  void set_BusSegmentEn(u32 node, u32 segbit)
 	pci_write_config32(dev, 0x68, dword);
 #endif
 }
+#endif
 
 #if !defined(__PRE_RAM__)
 static u32 get_io_addr_index(u32 nodeid, u32 linkn)
diff --git a/src/northbridge/amd/amdfam10/amdfam10_pci.c b/src/northbridge/amd/amdfam10/amdfam10_pci.c
index bc1bde08d0..d08a9718c7 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_pci.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_pci.c
@@ -32,6 +32,7 @@ static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index)
 	return dword;
 }
 
+#ifdef UNUSED_CODE
 static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32 data)
 {
 
@@ -40,6 +41,7 @@ static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, u32
 	pci_write_config32(dev, index_reg + 0x4, data);
 
 }
+#endif
 
 static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index)
 {
@@ -55,6 +57,7 @@ static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index)
 	return dword;
 }
 
+#ifdef UNUSED_CODE
 static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index, u32 data)
 {
 
@@ -69,5 +72,6 @@ static void pci_write_config32_index_wait(device_t dev, u32 index_reg, u32 index
 
 }
 #endif
+#endif
 
 
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index fc89ba39c4..f87428ba0c 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -17,12 +17,15 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+
+#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */
 static  void print_tx(const char *strval, u32 val)
 {
 #if CONFIG_DEBUG_RAM_SETUP
 	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
 #endif
 }
+#endif
 
 static  void print_t(const char *strval)
 {
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index 69869bf48c..21e06d1e2e 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -29,7 +29,7 @@
 
 /* mmconf is not ready */
 /* io_ext is not ready */
-static u32 cpu_init_detected(u8 nodeid)
+u32 cpu_init_detected(u8 nodeid)
 {
 	u32 htic;
 	device_t dev;
@@ -40,7 +40,7 @@ static u32 cpu_init_detected(u8 nodeid)
 	return !!(htic & HTIC_INIT_Detect);
 }
 
-static u32 bios_reset_detected(void)
+u32 bios_reset_detected(void)
 {
 	u32 htic;
 	htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL);
@@ -48,7 +48,7 @@ static u32 bios_reset_detected(void)
 	return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
 }
 
-static u32 cold_reset_detected(void)
+u32 cold_reset_detected(void)
 {
 	u32 htic;
 	htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL);
@@ -56,7 +56,7 @@ static u32 cold_reset_detected(void)
 	return !(htic & HTIC_ColdR_Detect);
 }
 
-static u32 other_reset_detected(void)	// other warm reset not started by BIOS
+u32 other_reset_detected(void)	// other warm reset not started by BIOS
 {
 	u32 htic;
 	htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL);
@@ -154,7 +154,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
 	return 0;
 }
 
-static u32 get_sblk(void)
+u32 get_sblk(void)
 {
 	u32 reg;
 	/* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */
@@ -163,7 +163,7 @@ static u32 get_sblk(void)
 }
 
 
-static u8 get_sbbusn(u8 sblk)
+u8 get_sbbusn(u8 sblk)
 {
 	return node_link_to_bus(0, sblk);
 }
diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h
index cc970c5906..dc7ef1bcab 100644
--- a/src/northbridge/amd/amdk8/amdk8.h
+++ b/src/northbridge/amd/amdk8/amdk8.h
@@ -11,6 +11,7 @@
 #ifdef __PRE_RAM__
 void showallroutes(int level, device_t dev);
 void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base);
+void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr);
 #endif
 
 #endif /* AMDK8_H */
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 5db9deafc4..91ff6b00ee 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -576,7 +576,7 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
 	return reset_needed;
 }
 
-#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) || defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55)
+#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) // || defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55)
 static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
 {
 	uint32_t dword;
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 8217464e37..efb7738306 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -19,7 +19,7 @@
 #define QRANK_DIMM_SUPPORT 0
 #endif
 
-static void setup_resource_map(const unsigned int *register_values, int max)
+void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
 //	printk(BIOS_DEBUG, "setting up resource map....");
@@ -2346,7 +2346,7 @@ static void set_sysinfo_in_ram(unsigned val)
 {
 }
 
-static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
+void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
 			  const uint16_t *spd_addr)
 {
 	int i;
diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h
index 8897ee71fa..7a548daf3b 100644
--- a/src/northbridge/amd/amdk8/raminit.h
+++ b/src/northbridge/amd/amdk8/raminit.h
@@ -13,6 +13,7 @@ struct mem_controller {
 
 struct sys_info;
 void exit_from_self(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo);
+void setup_resource_map(const unsigned int *register_values, int max);
 
 #if defined(__PRE_RAM__) && defined(RAMINIT_SYSINFO) && RAMINIT_SYSINFO == 1
 void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo);
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 6652783e66..01241f05c8 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -74,7 +74,7 @@
 	*/
 
 
-static void setup_resource_map(const unsigned int *register_values, int max)
+void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
 	for (i = 0; i < max; i += 3) {
@@ -3206,7 +3206,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
 
 }
 
-static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
+void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
 			  const uint16_t *spd_addr)
 {
 	int i;
diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c
index 36cb7cbea2..167088f200 100644
--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c
@@ -22,7 +22,9 @@
 
 static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstatA);
+#ifdef UNUSED_CODE
 static u32 GetScrubAddr_D(u32 Node);
+#endif
 static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat);
 
 
@@ -249,7 +251,7 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat,
 	}
 }
 
-
+#ifdef UNUSED_CODE
 static u32 GetScrubAddr_D(u32 Node)
 {
 	/* Get the current 40-bit Scrub ADDR address, scaled to 32-bits,
@@ -280,7 +282,7 @@ static u32 GetScrubAddr_D(u32 Node)
 
 	return val;		/* ScrubAddr[39:8] */
 }
-
+#endif
 
 static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat)
 {
diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c
index 1724ca0640..a2d08d194e 100644
--- a/src/northbridge/amd/amdmct/mct/mctpro_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c
@@ -313,7 +313,8 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct)
 	}
 }
 
-
+#ifdef UNUSED_CODE
+/* Callback not required */
 static u8 mct_AdjustDelay_D(struct DCTStatStruc *pDCTstat, u8 dly)
 {
 	u8 skip = 0;
@@ -323,7 +324,7 @@ static u8 mct_AdjustDelay_D(struct DCTStatStruc *pDCTstat, u8 dly)
 
 	return skip;
 }
-
+#endif
 
 static u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstat, u8 DQSDelay,
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index b6bd6dfa38..cc49aad2ae 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -19,6 +19,7 @@
 
 /* Call-backs */
 #include <delay.h>
+
 static u16 mctGet_NVbits(u8 index)
 {
 	u16 val = 0;
@@ -411,6 +412,7 @@ static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTSt
 #endif
 }
 
+#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
 static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val)
 {
 	if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) {
@@ -420,6 +422,7 @@ static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStr
 	}
 	return val;
 }
+#endif
 
 static void mctHookAfterAnyTraining(void)
 {
@@ -430,8 +433,9 @@ static u32 mctGetLogicalCPUID_D(u8 node)
 	return mctGetLogicalCPUID(node);
 }
 
+#if (CONFIG_DIMM_SUPPORT & 0x000F)!=0x0005 /* not needed for AMD_FAM10_DDR3 */
 static u8 mctSetNodeBoundary_D(void)
 {
 	return 0;
 }
-
+#endif
diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h
index bbdad3f3c1..8aae1a9aed 100644
--- a/src/northbridge/intel/i3100/i3100.h
+++ b/src/northbridge/intel/i3100/i3100.h
@@ -17,6 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#ifndef __I3100_H__
+#define __I3100_H__
+
 #define IURBASE	0X14
 #define MCHCFG0	0X50
 #define MCHSCRB	0X52
@@ -60,3 +63,10 @@
 /* DRC */
 #define DRC_NOECC_MODE        (0 << 20)
 #define DRC_72BIT_ECC         (1 << 20)
+
+
+#ifdef __GNUC__
+int bios_reset_detected(void);
+#endif
+
+#endif
diff --git a/src/northbridge/intel/i3100/reset_test.c b/src/northbridge/intel/i3100/reset_test.c
index 9cf4d89d7e..de86f8024d 100644
--- a/src/northbridge/intel/i3100/reset_test.c
+++ b/src/northbridge/intel/i3100/reset_test.c
@@ -6,7 +6,7 @@
 /* To see if I have already booted I check to see if memory
  * has been enabled.
  */
-static int bios_reset_detected(void)
+int bios_reset_detected(void)
 {
 	uint32_t dword;