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-rw-r--r--src/northbridge/amd/agesa/Kconfig11
-rw-r--r--src/northbridge/amd/agesa/family14/state_machine.c2
-rw-r--r--src/northbridge/amd/agesa/family15tn/state_machine.c2
-rw-r--r--src/northbridge/amd/agesa/family16kb/state_machine.c3
4 files changed, 18 insertions, 0 deletions
diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index 19b62f2cd8..1e0153b335 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -19,6 +19,17 @@ config NORTHBRIDGE_AMD_AGESA
if NORTHBRIDGE_AMD_AGESA
+config BOTTOMIO_POSITION
+ hex "Bottom of 32-bit IO space"
+ default 0x80000000
+ help
+ If PCI peripherals with big BARs are connected to the system
+ the bottom of the IO must be decreased to allocate such devices.
+
+ Declare the beginning of the 128MB-aligned MMIO region. This
+ option is useful when PCI peripherals requesting large address
+ ranges are present, for example, graphic cards.
+
config CONSOLE_VGA_MULTI
bool
default n
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c
index db923c5ec9..5b0040899a 100644
--- a/src/northbridge/amd/agesa/family14/state_machine.c
+++ b/src/northbridge/amd/agesa/family14/state_machine.c
@@ -48,6 +48,8 @@ void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)
void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
{
+ Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000,
+ MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8;
}
void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c
index 85bc2587ed..439e15d75d 100644
--- a/src/northbridge/amd/agesa/family15tn/state_machine.c
+++ b/src/northbridge/amd/agesa/family15tn/state_machine.c
@@ -18,6 +18,8 @@ void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)
void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
{
+ Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000,
+ MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8;
}
void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c
index a27962972a..be9adaff4f 100644
--- a/src/northbridge/amd/agesa/family16kb/state_machine.c
+++ b/src/northbridge/amd/agesa/family16kb/state_machine.c
@@ -20,6 +20,9 @@ void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
{
AGESA_STATUS status;
+ Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000,
+ MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8;
+
if (CONFIG(ENABLE_MRC_CACHE)) {
status = OemInitResume(&Post->MemConfig.MemContext);
if (status == AGESA_SUCCESS)