diff options
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdfam10/misc_control.c | 1 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/misc_control.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/e7520/pciexp_porta.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i3100/pciexp_porta.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i3100/pciexp_porta_ep80579.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i855pm/i855pm.h | 0 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/northbridge.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 12 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/raminit.h | 2 |
9 files changed, 12 insertions, 14 deletions
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index a321a656d2..5286529e13 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -30,7 +30,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <part/hard_reset.h> #include <pc80/mc146818rtc.h> #include <bitops.h> #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index efb44473a4..a1e88aa837 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -14,7 +14,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <part/hard_reset.h> +#include <reset.h> #include <pc80/mc146818rtc.h> #include <bitops.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/northbridge/intel/e7520/pciexp_porta.c b/src/northbridge/intel/e7520/pciexp_porta.c index ac833cf185..70e58076a7 100644 --- a/src/northbridge/intel/e7520/pciexp_porta.c +++ b/src/northbridge/intel/e7520/pciexp_porta.c @@ -6,7 +6,7 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" -#include <part/hard_reset.h> +#include <reset.h> typedef struct northbridge_intel_e7520_config config_t; diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c index 8cafb28f38..da010f3703 100644 --- a/src/northbridge/intel/i3100/pciexp_porta.c +++ b/src/northbridge/intel/i3100/pciexp_porta.c @@ -28,7 +28,7 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" -#include <part/hard_reset.h> +#include <reset.h> typedef struct northbridge_intel_i3100_config config_t; diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index 9fbd5391e1..dbc1b5fdbb 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -28,7 +28,7 @@ #include <device/pciexp.h> #include <arch/io.h> #include "chip.h" -#include <part/hard_reset.h> +#include <reset.h> typedef struct northbridge_intel_i3100_config config_t; diff --git a/src/northbridge/intel/i855pm/i855pm.h b/src/northbridge/intel/i855pm/i855pm.h deleted file mode 100644 index e69de29bb2..0000000000 --- a/src/northbridge/intel/i855pm/i855pm.h +++ /dev/null diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 4ccffc6b55..5f71e19a90 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -31,8 +31,9 @@ #include <boot/tables.h> #include "chip.h" #include "i945.h" +#include <arch/coreboot_tables.h> -int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base, u32 *len) { device_t dev; u32 pciexbar_reg; diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 124ef147c3..be63e7adcc 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -398,12 +398,8 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) die("No memory installed.\n"); } - /* The chipset might be able to do this. What the heck, legacy bios - * just beeps when a single DIMM is in the Channel 1 socket. So let's - * not bother until someone needs this enough to cope with it. - */ if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { - printk_err("Channel 0 has no memory populated. This setup is not usable. Please move the DIMM.\n"); + printk_info("Channel 0 has no memory populated.\n"); } } @@ -454,7 +450,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 { int i, j, idx; int lowest_common_cas = 0; - int max_ram_speed; + int max_ram_speed = 0; const u8 ddr2_speeds_table[] = { 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ @@ -1593,7 +1589,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo) if (sysinfo->banks[i] != 8) continue; - printk_spew("DIMM%d has 8 banks.\n"); + printk_spew("DIMM%d has 8 banks.\n", i); if (i & 1) MCHBAR16(off32) |= 0x50; @@ -2572,7 +2568,7 @@ static void sdram_power_management(struct sys_info *sysinfo) reg8 |= (1 << 2); pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8); -#if C2_SELF_REFRESH_DISABLE +#ifdef C2_SELF_REFRESH_DISABLE if (integrated_graphics) { printk_debug("C2 self-refresh with IGD\n"); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 070b913947..7ebbd7c2c3 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -67,4 +67,6 @@ struct sys_info { } __attribute__ ((packed)); +void receive_enable_adjust(struct sys_info *sysinfo); + #endif /* RAMINIT_H */ |