diff options
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdfam10/misc_control.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mctecc_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/lx/northbridgeinit.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/raminit.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/raminit.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/raminit_tables.c | 2 | ||||
| -rw-r--r-- | src/northbridge/via/vx900/raminit_ddr3.c | 8 |
10 files changed, 15 insertions, 15 deletions
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 028f6af460..8323c1e20f 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -19,7 +19,7 @@ /* Turn off machine check triggers when reading * pci space where there are no devices. - * This is necessary when scaning the bus for + * This is necessary when scanning the bus for * devices which is done by the kernel */ diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 18774ebe7a..7be63533a9 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -68,7 +68,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat); * (aka SW memhole, cs hoisting, etc..).To init ECC memory on this node, the * scrubber is used in two steps. First, the Dram Limit for the node is adjusted * down to the bottom of the gap, and that ECC dram is initialized. Second, the - * orignal Limit is restored, the Scrub base is set to 4GB, and scrubber is + * original Limit is restored, the Scrub base is set to 4GB, and scrubber is * allowed to run until the Scrub Addr wraps around to zero. */ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 31c23b9445..20a636e480 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -83,7 +83,7 @@ static uint8_t is_fam15h(void) * (aka SW memhole, cs hoisting, etc..).To init ECC memory on this node, the * scrubber is used in two steps. First, the Dram Limit for the node is adjusted * down to the bottom of the gap, and that ECC dram is initialized. Second, the - * orignal Limit is restored, the Scrub base is set to 4GB, and scrubber is + * original Limit is restored, the Scrub base is set to 4GB, and scrubber is * allowed to run until the Scrub Addr wraps around to zero. */ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index ed942eaff2..f62aa1568a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -924,7 +924,7 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui u8 WrLvOdt1 = 0; if (is_fam15h()) { - /* On Family15h processors, the value for the specific CS being targetted + /* On Family15h processors, the value for the specific CS being targeted * is taken from F2x238 / F2x23C as appropriate, then loaded into F2x9C_x0000_0008 */ diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index 3d9ff3ec14..bcf3ddc7fd 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -170,7 +170,7 @@ u16 mctGet_NVbits(u8 index) case NV_SPDCHK_RESTRT: val = 0; /* Exit current node initialization if any DIMM has SPD checksum error */ //val = 1; /* Ignore faulty SPD checksum (DIMM will still be disabled), continue current node initialization */ - //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node intialization */ + //val = 2; /* Override faulty SPD checksum (DIMM will be enabled), continue current node initialization */ if (get_option(&nvram, "dimm_spd_checksum") == CB_SUCCESS) val = nvram & 0x3; diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 6c2efb320c..c7db156ceb 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -122,7 +122,7 @@ static void SysmemInit(struct gliutable *gl) int sizembytes, sizebytes; /* - * Figure out how much RAM is in the machine and alocate all to the + * Figure out how much RAM is in the machine and allocate all to the * system. We will adjust for SMM now and Frame Buffer later. */ sizembytes = sizeram(); @@ -272,7 +272,7 @@ static void GLPCIInit(void) * base of 1M and top of around 256M */ /* we have to create a page-aligned (4KB page) address for base and top */ - /* So we need a high page aligned addresss (pah) and low page aligned address (pal) + /* So we need a high page aligned address (pah) and low page aligned address (pal) * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12 */ pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 08f954d057..03f617c6a3 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -869,7 +869,7 @@ static void configure_dram_control_mode(const timings_t *const timings, const di static void rcomp_initialization(const stepping_t stepping, const int sff) { - /* Programm RCOMP codes. */ + /* Program RCOMP codes. */ if (sff) die("SFF platform unsupported in RCOMP initialization.\n"); /* Values are for DDR3. */ @@ -1825,7 +1825,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) /* Some last optimizations. */ dram_optimizations(timings, dimms); - /* Mark raminit beeing finished. :-) */ + /* Mark raminit being finished. :-) */ u8 tmp8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2) & ~(1 << 7); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, tmp8); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 66f0a10419..2a1e34cea2 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1972,7 +1972,7 @@ static void sdram_rcven(struct sysinfo *s) MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) | (curcoarse << 16); if (curcoarse == 0) { - PRINTK_DEBUG("Error: DQS didnt hit 0\n"); + PRINTK_DEBUG("Error: DQS did not hit 0\n"); break; } } diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index 401af15cd8..ebd1562bde 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -332,7 +332,7 @@ const u32 ddr3_c2_tab[2][3][6][2] = { /* [n-mode][ddr3 freq][CAS][reg] */ {0x0189, 0x000aaa}, /* CAS = 5 */ {0x0189, 0x101aaa}, /* CAS = 6 */ {0x0000, 0x000000}, /* CAS = 7 - Not supported */ - {0x0000, 0x000000} /* CAS = 8 - Not suppported */ + {0x0000, 0x000000} /* CAS = 8 - Not supported */ }, { /* DDR3 1067 */ {0x0000, 0x000000}, /* CAS = 5 - Not supported */ diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index eec4aa357f..17a87bbe97 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -42,7 +42,7 @@ * * The capture window is not calibrated, but preset. Whether that preset is * universal or frequency dependent, and whether it is board-specific or not is - * not yet clear. @see vx900_dram_calibrate_recieve_delays(). + * not yet clear. @see vx900_dram_calibrate_receive_delays(). * * 4GBit and 8GBit modules may not work. This is untested. Modules with 11 * column address bits are not tested. @see vx900_dram_map_row_col_bank() @@ -166,7 +166,7 @@ static pci_reg8 mcu_init_config[] = { {0x66, 0x80}, /* DRAM Queue / Arbitration */ {0x69, 0xc6}, /* Bank Control: 8 banks, high priority refresh */ {0x6a, 0xfc}, /* DRAMC Request Reorder Control */ - {0x6e, 0x38}, /* Burst lenght: 8, burst-chop: enable */ + {0x6e, 0x38}, /* Burst length: 8, burst-chop: enable */ {0x73, 0x04}, /* Close All Pages Threshold */ /* The following need to be dynamically asserted */ @@ -1224,7 +1224,7 @@ static void vx900_rxdqs_adjust(delay_range * dly) vx900_write_0x78_0x7f(dly->avg); } -static void vx900_dram_calibrate_recieve_delays(vx900_delay_calib * delays, +static void vx900_dram_calibrate_receive_delays(vx900_delay_calib * delays, u8 pinswap) { size_t n_tries = 0; @@ -1417,7 +1417,7 @@ static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl, /* Only run on first rank, remember? */ break; } - vx900_dram_calibrate_recieve_delays(&delay_cal, + vx900_dram_calibrate_receive_delays(&delay_cal, ranks->flags[i].pins_mirrored); printram("RX DQS calibration results\n"); dump_delay_range(delay_cal.rx_dqs); |